Keltcher; Chetana N.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Keltcher; Chetana N..The latest application filed is for "apparatus and method for resynchronization prediction with variable upgrade and downgrade capability".

Company Profile

1.10.5

Keltcher; Chetana N. - Lexington MA
Keltcher; Chetana N. - Sunnyvale CA
Keltcher; Chetana N. - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Apparatus and method for resynchronization prediction with variable upgrade and downgrade capability Grant 11,099,846 - Ramani , et al. August 24, 2	2021-08-24
Apparatus And Method For Resynchronization Prediction With Variable Upgrade And Downgrade Capability App 20190391808 - Ramani; Krishnan V. ; et al.	2019-12-26
Hierarchical clock control using hysterisis and threshold management Grant 9,494,997 - Kothari , et al. November 15, 2	2016-11-15
Hierarchical Clock Control Using Hysterisis And Threshold Management App 20150362978 - Kothari; Kulin N. ; et al.	2015-12-17
Vector Processing System App 20130185496 - Hessel; Richard Edward ; et al.	2013-07-18
Vector processor system Grant 8,356,144 - Hessel , et al. January 15, 2	2013-01-15
Vector Processor System App 20090300323 - Hessel; Richard ; et al.	2009-12-03
Vector processor Grant 7,543,119 - Hessel , et al. June 2, 2	2009-06-02
Vector processor App 20070255894 - Hessel; Richard Edward ; et al.	2007-11-01
Piggybacking of ECC corrections behind loads Grant 7,043,679 - Keltcher , et al. May 9, 2	2006-05-09
Using microcode to correct ECC errors in a processor Grant 6,934,903 - Keltcher , et al. August 23, 2	2005-08-23
Efficient method for mode change detection and synchronization Grant 6,898,697 - Gao , et al. May 24, 2	2005-05-24
Memory address checking in a proccesor that support both a segmented and a unsegmented address space Grant 6,807,616 - McGrath , et al. October 19, 2	2004-10-19
System for implementing a register free-list by using swap bit to select first or second register tag in retire queue Grant 6,425,072 - Meier , et al. July 23, 2	2002-07-23

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.