Keller; Eric R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Keller; Eric R..The latest application filed is for "apparatus, method, and system to dynamically deploy wireless infrastructure".

Company Profile

2.30.4

Keller; Eric R. - Louisville CO
Keller; Eric R. - Boulder CO

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Apparatus, method, and system to dynamically deploy wireless infrastructure Grant 11,429,407 - Smith , et al. August 30, 2	2022-08-30
Apparatus, Method, And System To Dynamically Deploy Wireless Infrastructure App 20190272187 - Smith; Jonathan M. ; et al.	2019-09-05
Dynamically deployable wireless infrastructure in cloud environment Grant 10,223,139 - Smith , et al.	2019-03-05
Apparatus, Method, And System To Dynamically Deploy Wireless Infrastructure App 20140282544 - Smith; Jonathan M. ; et al.	2014-09-18
Method for scheduling a network packet processor Grant 8,284,772 - James-Roxby , et al. October 9, 2	2012-10-09
Method for message processing on a programmable logic device Grant 8,065,130 - Brebner , et al. November 22, 2	2011-11-22
Generation of executable threads having source code specifications that describe network packets Grant 8,032,874 - Keller , et al. October 4, 2	2011-10-04
Pipeline for processing network packets Grant 7,990,867 - Keller , et al. August 2, 2	2011-08-02
Thread circuits and a broadcast channel in programmable logic Grant 7,823,162 - Keller , et al. October 26, 2	2010-10-26
Method for simulating a processor of network packets Grant 7,792,117 - Keller , et al. September 7, 2	2010-09-07
Circuit for modification of a network packet by insertion or removal of a data segment Grant 7,788,402 - Keller , et al. August 31, 2	2010-08-31
Generation of a specification of a network packet processor Grant 7,784,014 - Brebner , et al. August 24, 2	2010-08-24
Method and apparatus for multithreading on a programmable logic device Grant 7,770,179 - James-Roxby , et al. August 3, 2	2010-08-03
Method and apparatus for configuring a processor embedded in an integrated circuit for use as a logic element Grant 7,698,449 - Keller , et al. April 13, 2	2010-04-13
Bootable integrated circuit device for readback encoding of configuration data Grant 7,689,726 - Sundararajan , et al. March 30, 2	2010-03-30
Memory arrangement for message processing by a plurality of threads Grant 7,653,895 - James-Roxby , et al. January 26, 2	2010-01-26
Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip Grant 7,574,680 - Kulkarni , et al. August 11, 2	2009-08-11
Method for message processing on a programmable logic device Grant 7,552,042 - Brebner , et al. June 23, 2	2009-06-23
Using redundant routing to reduce susceptibility to single event upsets in PLD designs Grant 7,386,826 - Keller , et al. June 10, 2	2008-06-10
Bootable programmable logic device for internal decoding of encoded configuration data Grant 7,328,335 - Sundararajan , et al. February 5, 2	2008-02-05
Reconfiguration of a programmable logic device using internal control Grant 7,227,378 - Blodget , et al. June 5, 2	2007-06-05
Method and apparatus for a programmable interface of a soft platform on a programmable logic device Grant 7,228,520 - Keller , et al. June 5, 2	2007-06-05
Method and apparatus for application-specific programmable memory architecture and interconnection network on a chip Grant 7,185,309 - Kulkarni , et al. February 27, 2	2007-02-27
Using an embedded processor to implement a finite state machine Grant 7,131,077 - James-Roxby , et al. October 31, 2	2006-10-31
Methods of reducing the susceptibility of PLD designs to single event upsets Grant 7,111,215 - Keller , et al. September 19, 2	2006-09-19
Method of and apparatus for enabling a hardware module to interact with a data structure Grant 7,076,596 - Keller , et al. July 11, 2	2006-07-11
Method of using a hardware library in a programmable logic device Grant 7,028,283 - Keller , et al. April 11, 2	2006-04-11
Configurable address generator and circuit using same Grant 7,010,664 - Ballagh , et al. March 7, 2	2006-03-07
Reconfiguration of a programmable logic device using internal control App 20050193358 - Blodget, Brandon J. ; et al.	2005-09-01
Reconfiguration of a programmable logic device using internal control Grant 6,920,627 - Blodget , et al. July 19, 2	2005-07-19
Method and system for generating a circuit design including a peripheral component connected to a bus Grant 6,883,147 - Ballagh , et al. April 19, 2	2005-04-19
Reconfiguration of a programmable logic device using internal control App 20040117755 - Blodget, Brandon J. ; et al.	2004-06-17
Method and apparatus for defining and modifying connections between logic cores implemented on programmable logic devices Grant 6,725,441 - Keller , et al. April 20, 2	2004-04-20
Run-time routing for programmable logic devices Grant 6,487,709 - Keller , et al. November 26, 2	2002-11-26

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