Kelkar; Nikhil Vishwanath

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kelkar; Nikhil Vishwanath.The latest application filed is for "method of making a stacked inductor-electronic package".

Company Profile

1.28.16

Kelkar; Nikhil Vishwanath - Saratoga CA
Kelkar; Nikhil Vishwanath - San Jose CA US
Kelkar; Nikhil Vishwanath - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method Of Making A Stacked Inductor-electronic Package App 20200266159 - MOUSSAOUI; ZAKI ; et al.	2020-08-20
Stacked Inductor-electronic Package Assembly And Technique For Manufacturing Same App 20170179048 - MOUSSAOUI; ZAKI ; et al.	2017-06-22
Packaged Circuit With A Lead Frame And Laminate Substrate App 20170162488 - Yin; Jian ; et al.	2017-06-08
Packaged circuit with a lead frame and laminate substrate Grant 9,613,889 - Yin , et al. April 4, 2	2017-04-04
Stacked inductor-electronic package assembly and technique for manufacturing same Grant 9,607,917 - Moussaoui , et al. March 28, 2	2017-03-28
Packaged Circuit With A Lead Frame And Laminate Substrate App 20150194370 - Yin; Jian ; et al.	2015-07-09
Method of manufacturing a packaged circuit including a lead frame and a laminate substrate Grant 9,012,267 - Yin , et al. April 21, 2	2015-04-21
Package leadframe for dual side assembly Grant 8,951,847 - Kelkar , et al. February 10, 2	2015-02-10
Packaged semiconductor devices including pre-molded lead-frame structures, and related methods and systems Grant 8,946,875 - Kelkar , et al. February 3, 2	2015-02-03
Packaged Circuit With A Lead Frame And Laminate Substrate App 20130313694 - Yin; Jian ; et al.	2013-11-28
System And Methods For Wire Bonding App 20130270701 - Cruz; Randolph ; et al.	2013-10-17
Bond pad configurations for semiconductor dies Grant 8,558,396 - Kelkar , et al. October 15, 2	2013-10-15
Packaged Semiconductor Devices, And Related Methods And Systems App 20130187260 - Kelkar; Nikhil Vishwanath ; et al.	2013-07-25
Package Leadframe For Dual Side Assembly App 20130181332 - Kelkar; Nikhil Vishwanath ; et al.	2013-07-18
Leadframe structures for semiconductor packages Grant 8,445,998 - Kim , et al. May 21, 2	2013-05-21
Bond Pad Configurations For Semiconductor Dies App 20130015592 - Kelkar; Nikhil Vishwanath ; et al.	2013-01-17
Clear Layer Isolation App 20120290255 - Kelkar; Nikhil Vishwanath ; et al.	2012-11-15
Power-supply Module With Electromagnetic-interference (emi) Shielding, Cooling, Or Both Shielding And Cooling, Along Two Or More Sides App 20120063038 - YIN; Jian ; et al.	2012-03-15
Stacked Inductor-electronic Package Assembly And Technique For Manufacturing Same App 20110134613 - MOUSSAOUI; Zaki ; et al.	2011-06-09
Leadframe structures for semiconductor packages Grant 7,714,415 - Kim , et al. May 11, 2	2010-05-11
Semiconductor devices having a back surface protective coating Grant 7,642,175 - Patwardhan , et al. January 5, 2	2010-01-05
Leadframe structures for semiconductor packages App 20070252247 - Kim; Young-Gon ; et al.	2007-11-01
Wafer level package design that facilitates trimming and testing Grant 7,282,375 - Kelkar October 16, 2	2007-10-16
Wafer level chip scale package Grant 7,241,643 - Kelkar , et al. July 10, 2	2007-07-10
Semiconductor devices having a back surface protective coating Grant 7,135,385 - Patwardhan , et al. November 14, 2	2006-11-14
Marking wafers using pigmentation in a mounting tape Grant 7,015,064 - Patwardhan , et al. March 21, 2	2006-03-21
Marking semiconductor devices through a mount tape Grant 6,972,244 - Patwardhan , et al. December 6, 2	2005-12-06
Semiconductor wafer having a bottom surface protective coating Grant RE38,789 - Kao , et al. September 6, 2	2005-09-06
Wafer level chip scale package Grant 6,900,532 - Kelkar , et al. May 31, 2	2005-05-31
Chip scale package with compliant leads Grant 6,900,110 - Takiar , et al. May 31, 2	2005-05-31
Encapsulant material applicator for semiconductor wafers and method of use thereof Grant 6,730,170 - Pham , et al. May 4, 2	2004-05-04
Chip scale package with compliant leads Grant 6,521,970 - Takiar , et al. February 18, 2	2003-02-18
Barrier pad for wafer level chip scale packages Grant 6,462,426 - Kelkar , et al. October 8, 2	2002-10-08
Metal coated markings on integrated circuit devices Grant 6,448,632 - Takiar , et al. September 10, 2	2002-09-10
Semiconductor wafer having a bottom surface protective coating Grant 6,175,162 - Kao , et al. January 16, 2	2001-01-16
Surface mount die: wafer level chip-scale package and process for making the same Grant 6,075,290 - Schaefer , et al. June 13, 2	2000-06-13
Semiconductor wafer having a bottom surface protective coating Grant 6,023,094 - Kao , et al. February 8, 2	2000-02-08

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