loadpatents
name:-0.0022768974304199
name:-0.094062089920044
name:-0.00076007843017578
Keeley; James W. Patent Filings

Keeley; James W.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Keeley; James W..The latest application filed is for "bridge apparatus and methods for coupling multiple non-fibre channel devices to a fibre channel arbitrated loop".

Company Profile
0.27.2
  • Keeley; James W. - Hollis NH US
  • Keeley; James W. - Nashua NH
  • Keeley; James W. - Hudson NH
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Apparatus and methods for access fairness for a multiple target bridge/router in a fibre channel arbitrated loop system
Grant 8,379,665 - Keeley , et al. February 19, 2
2013-02-19
Bridge apparatus and methods for coupling multiple non-fibre channel devices to a fibre channel arbitrated loop
Grant 8,116,330 - Keeley , et al. February 14, 2
2012-02-14
Apparatus And Methods For Access Fairness For A Multiple Target Bridge/router In A Fibre Channel Arbitrated Loop System
App 20100303084 - Keeley; James W. ;   et al.
2010-12-02
Bridge Apparatus And Methods For Coupling Multiple Non-fibre Channel Devices To A Fibre Channel Arbitrated Loop
App 20100303085 - Keeley; James W. ;   et al.
2010-12-02
Bus interface state machines with independent access to memory, processor and registers for concurrent processing of different types of requests
Grant 5,471,638 - Keeley November 28, 1
1995-11-28
Means for providing a graceful power shut-down capability in a multiprocessor system having certain processors not inherently having a power shut-down capability
Grant 5,367,697 - Barlow , et al. November 22, 1
1994-11-22
Processing unit having multiple synchronous bus for sharing access and regulating system bus access to synchronous bus
Grant 5,341,508 - Keeley , et al. August 23, 1
1994-08-23
Bus controller having state machine for translating commands and controlling accesses from system bus to synchronous bus having different bus protocols
Grant 5,341,495 - Joyce , et al. August 23, 1
1994-08-23
Microprocessor bus interface protocol analyzer
Grant 5,293,384 - Keeley , et al. March 8, 1
1994-03-08
Method and apparatus for avoiding processor deadly embrace in a multiprocessor system
Grant 5,283,870 - Joyce , et al. February 1, 1
1994-02-01
Multiprocessor system with centralized initialization, testing and monitoring of the system and providing centralized timing
Grant 5,274,797 - Barlow , et al. December 28, 1
1993-12-28
Method and apparatus for performing health tests of units of a data processing system
Grant 5,210,757 - Barlow , et al. May 11, 1
1993-05-11
Recovery method and apparatus for a pipelined processing unit of a multiprocessor system
Grant 5,193,181 - Barlow , et al. March 9, 1
1993-03-09
Apparatus for loading and verifying a control store memory of a central subsystem
Grant 4,910,666 - Nibby, Jr. , et al. March 20, 1
1990-03-20
Data processing system with a fast interrupt
Grant 4,839,800 - Barlow , et al. June 13, 1
1989-06-13
Cache resiliency in processing a variety of address faults
Grant 4,833,601 - Barlow , et al. May 23, 1
1989-05-23
Multiprocessor level change synchronization apparatus
Grant 4,802,087 - Keeley , et al. January 31, 1
1989-01-31
Address transform method and apparatus for transferring addresses
Grant 4,799,222 - Barlow , et al. January 17, 1
1989-01-17
Multiprocessor coherent cache system including two level shared cache with separately allocated processor storage locations and inter-level duplicate entry replacement
Grant 4,785,395 - Keeley November 15, 1
1988-11-15
Read in process memory apparatus
Grant 4,768,148 - Keeley , et al. August 30, 1
1988-08-30
Resilient bus system
Grant 4,764,862 - Barlow , et al. August 16, 1
1988-08-16
Resilient bus system
Grant 4,763,243 - Barlow , et al. August 9, 1
1988-08-09
Channel number priority assignment apparatus
Grant 4,724,519 - Barlow , et al. February 9, 1
1988-02-09
Test apparatus for testing a multilevel cache system with graceful degradation capability
Grant 4,686,621 - Keeley , et al. August 11, 1
1987-08-11
Enable/disable control checking apparatus
Grant 4,667,288 - Keeley , et al. May 19, 1
1987-05-19
Shared interface apparatus for testing the memory sections of a cache unit
Grant 4,575,792 - Keeley March 11, 1
1986-03-11
Directory test error mode control apparatus
Grant 4,562,536 - Keeley , et al. December 31, 1
1985-12-31
Multilevel cache system with graceful degradation capability
Grant 4,464,717 - Keeley , et al. August 7, 1
1984-08-07

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