Keech; Ryan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Keech; Ryan.The latest application filed is for "top gate recessed channel cmos thin film transistor in the back end of line and methods of fabrication".

Company Profile

7.3.22

Keech; Ryan - Portland OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Top Gate Recessed Channel Cmos Thin Film Transistor In The Back End Of Line And Methods Of Fabrication App 20220223519 - Dewey; Gilbert ; et al.	2022-07-14
Self-aligned Interconnect Structures And Methods Of Fabrication App 20220199468 - Jun; Kimin ; et al.	2022-06-23
Source & Drain Dopant Diffusion Barriers For N-type Germanium Transistors App 20220199402 - Ganguly; Koustav ; et al.	2022-06-23
Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication Grant 11,328,988 - Dewey , et al. May 10, 2	2022-05-10
Low Resistance Approaches For Fabricating Contacts And The Resulting Structures App 20220102521 - DEWEY; Gilbert ; et al.	2022-03-31
Three-dimensional Integrated Circuits (3dics) Including Bottom Gate Mos Transistors With Monocrystalline Channel Material App 20220093586 - Huang; Cheng-Ying ; et al.	2022-03-24
Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material Grant 11,244,943 - Huang , et al. February 8, 2	2022-02-08
Contact Resistance Reduction In Transistor Devices With Metallization On Both Sides App 20210408246 - GANGULY; Koustav ; et al.	2021-12-30
Gate-all-around Integrated Circuit Structures Having Strained Source Or Drain Structures On Insulator App 20210408283 - AGRAWAL; Ashish ; et al.	2021-12-30
Gate-all-around Integrated Circuit Structures Having Strained Dual Nanoribbon Channel Structures App 20210407996 - AGRAWAL; Ashish ; et al.	2021-12-30
Gate-all-around Integrated Circuit Structures Having Strained Source Or Drain Structures On Gate Dielectric Layer App 20210408284 - AGRAWAL; Ashish ; et al.	2021-12-30
Three-dimensional integrated circuits (3DICs) including upper-level transistors with epitaxial source and drain material Grant 11,164,785 - Agrawal , et al. November 2, 2	2021-11-02
Three-dimensional Integrated Circuits (3dics) Including Bottom Gate Mos Transistors With Monocrystalline Channel Material App 20210202476 - Huang; Cheng-Ying ; et al.	2021-07-01
Top Gate Recessed Channel Cmos Thin Film Transistor In The Back End Of Line And Methods Of Fabrication App 20210202378 - Dewey; Gilbert ; et al.	2021-07-01
Three-dimensional Integrated Circuits (3dics) Including Upper-level Transistors With Epitaxial Source & Drain Material App 20210202319 - Agrawal; Ashish ; et al.	2021-07-01
High Aspect Ration Source Or Drain Structures With Abrupt Dopant Profile App 20210091181 - KEECH; Ryan ; et al.	2021-03-25
Source Or Drain Structures For Germanium N-channel Devices App 20200313001 - KEECH; Ryan ; et al.	2020-10-01
Source Or Drain Structures With Vertical Trenches App 20200312842 - KEECH; Ryan ; et al.	2020-10-01
Source Or Drain Structures With Phosphorous And Arsenic Co-dopants App 20200312958 - MURTHY; Anand ; et al.	2020-10-01
Arsenic-doped Epitaxial Source/drain Regions For Nmos App 20200105754 - Murthy; Anand ; et al.	2020-04-02
Vertically Stacked Cmos With Upfront M0 Interconnect App 20200098921 - RACHMADY; Willy ; et al.	2020-03-26

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