Ke; Yanjing

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ke; Yanjing.The latest application filed is for "methods and apparatus for performing clock and data duty cycle correction in a high-speed link".

Company Profile

1.16.7

Ke; Yanjing - Union City CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods and apparatus for performing clock and data duty cycle correction in a high-speed link Grant 11,115,177 - Ke , et al. September 7, 2	2021-09-07
Methods And Apparatus For Performing Clock And Data Duty Cycle Correction In A High-speed Link App 20190215146 - Ke; Yanjing ; et al.	2019-07-11
Method and apparatus for phase-aligned 2X frequency clock generation Grant 10,340,904 - Ke	2019-07-02
Method And Apparatus For Phase-aligned 2x Frequency Clock Generation App 20170373675 - KE; Yanjing	2017-12-28
Systems and methods for reducing power supply noise or jitter Grant 9,748,934 - Oh , et al. August 29, 2	2017-08-29
Circuits and methods for adjusting the voltage swing of a signal Grant 9,231,631 - Ke , et al. January 5, 2	2016-01-05
Latency built-in self-test Grant 9,100,112 - Leong , et al. August 4, 2	2015-08-04
Systems and methods for digital calibration of successive-approximation-register analog-to-digital converter Grant 9,054,721 - Li , et al. June 9, 2	2015-06-09
Apparatus and methods for on-die instrumentation Grant 8,837,571 - Ke , et al. September 16, 2	2014-09-16
Systems and methods for digital calibration of successive-approximation-register analog-to-digital converter Grant 8,674,862 - Li , et al. March 18, 2	2014-03-18
Techniques for reducing duty cycle distortion in periodic signals Grant 8,416,001 - Ding , et al. April 9, 2	2013-04-09
Configurable buffer circuits and methods Grant 8,395,421 - Ding , et al. March 12, 2	2013-03-12
Techniques for Reducing Duty Cycle Distortion in Periodic Signals App 20120256670 - Ding; Weiqi ; et al.	2012-10-11
Configurable buffer circuits and methods Grant 8,174,294 - Ding , et al. May 8, 2	2012-05-08
Clock data recovery (CDR) system using interpolator and timing loop module Grant 7,861,105 - Ke , et al. December 28, 2	2010-12-28
PLLS covering wide operating frequency ranges Grant 7,692,497 - Hao , et al. April 6, 2	2010-04-06
Data recovery (CDR) architecture using interpolator and timing loop module App 20080320324 - Ke; Yanjing ; et al.	2008-12-25
PLLS covering wide operating frequency ranges App 20080191760 - Hao; Jianbin ; et al.	2008-08-14
Pre-Clock/Data Recovery Multiplexing of Input Signals in a HDMI Video Receiver App 20080117984 - Hao; Jianbin ; et al.	2008-05-22
Multiplexed DVI and displayport transmitter App 20080111919 - Hao; Jianbin ; et al.	2008-05-15

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