loadpatents
name:-0.017170906066895
name:-0.021649122238159
name:-0.0061650276184082
Kazior; Thomas E. Patent Filings

Kazior; Thomas E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kazior; Thomas E..The latest application filed is for "group iii-v semiconductor structures having crystalline regrowth layers and methods for forming such structures".

Company Profile
5.23.18
  • Kazior; Thomas E. - Sudbury MA
  • Kazior; Thomas E. - Arlington VA
  • Kazior; Thomas E. - Waltham MA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Group Iii-v Semiconductor Structures Having Crystalline Regrowth Layers And Methods For Forming Such Structures
App 20220140126 - LaRoche; Jeffrey R. ;   et al.
2022-05-05
Electrode structure for field effect transistor
Grant 11,239,326 - LaRoche , et al. February 1, 2
2022-02-01
Nitride structures having low capacitance gate contacts integrated with copper damascene structures
Grant 11,177,216 - LaRoche , et al. November 16, 2
2021-11-16
Low-Temperature Deposition of High-Quality Aluminum Nitride Films for Heat Spreading Applications
App 20210249331 - Ueda; Scott ;   et al.
2021-08-12
Wafer structure with mode suppression
Grant 10,930,742 - Kazemi , et al. February 23, 2
2021-02-23
Wafer Structure With Mode Suppression
App 20200219982 - Kazemi; Hooman ;   et al.
2020-07-09
Nitride Structures Having Low Capacitance Gate Contacts Integrated With Copper Damascene Structures
App 20200083167 - LaRoche; Jeffrey R. ;   et al.
2020-03-12
Electrode Structure For Field Effect Transistor
App 20190237554 - LaRoche; Jeffrey R. ;   et al.
2019-08-01
Reconstituted Wafer Structure
App 20190165108 - Kazemi; Hooman ;   et al.
2019-05-30
Electrode Structure For Field Effect Transistor
App 20190097001 - LaRoche; Jeffrey R. ;   et al.
2019-03-28
Nitride structure having gold-free contact and methods for forming such structures
Grant 10,224,285 - LaRoche , et al.
2019-03-05
Nitride structure having gold-free contact and methods for forming such structures
Grant 10,096,550 - LaRoche , et al. October 9, 2
2018-10-09
Nitride Structure Having Gold-free Contact And Methods For Forming Such Structures
App 20180240753 - LaRoche; Jeffrey R. ;   et al.
2018-08-23
Nitride Structure Having Gold-free Contact And Methods For Forming Such Structures
App 20180240754 - LaRoche; Jeffrey R. ;   et al.
2018-08-23
Methods and structures for forming microstrip transmission lines on thin silicon carbide on insulator (SICOI) wafers
Grant 9,761,445 - LaRoche , et al. September 12, 2
2017-09-12
Microwave integrated circuit (MMIC) damascene electrical interconnect for microwave energy transmission
Grant 9,478,508 - LaRoche , et al. October 25, 2
2016-10-25
Methods And Structures For Forming Microstrip Transmission Lines On Thin Silicon Carbide On Insulator (sicoi) Wafers
App 20160211136 - LaRoche; Jeffrey R. ;   et al.
2016-07-21
Double heterojunction group III-nitride structures
Grant 9,231,064 - Reza , et al. January 5, 2
2016-01-05
Method For Reducing Growth Of Non-uniformities And Autodoping During Column Iii-v Growth Into Dielectric Windows
App 20150059640 - LaRoche; Jeffrey R. ;   et al.
2015-03-05
Method and structure having monolithic heterogeneous integration of compound semiconductors with elemental semiconductor
Grant 8,575,666 - LaRoche , et al. November 5, 2
2013-11-05
Passivation layer for a circuit device and method of manufacture
Grant RE44,303 - Bedinger , et al. June 18, 2
2013-06-18
Gold-free ohmic contacts
Grant 8,466,555 - Chelakara , et al. June 18, 2
2013-06-18
Method And Structure Having Monolithic Heterogeneous Integration Of Compound Semiconductors With Elemental Semiconductor
App 20130082281 - LaRoche; Jeffrey R. ;   et al.
2013-04-04
Gold-free Ohmic Contacts
App 20120305931 - Chelakara; Ram V. ;   et al.
2012-12-06
Passivation layer for a circuit device and method of manufacture
Grant 7,902,083 - Bedinger , et al. March 8, 2
2011-03-08
Passivation layer for a circuit device and method of manufacture
Grant 7,767,589 - Bedinger , et al. August 3, 2
2010-08-03
Passivation Layer for a Circuit Device and Method of Manufacture
App 20100120254 - Bedinger; John M. ;   et al.
2010-05-13
Method For Packaging Semiconductors At A Wafer Level
App 20080308922 - Zhang; Yiwen ;   et al.
2008-12-18
Passivation Layer for a Circuit Device and Method of Manufacture
App 20080185174 - Bedinger; John M. ;   et al.
2008-08-07
MMIC having back-side multi-layer signal routing
Grant 7,387,958 - McCarroll , et al. June 17, 2
2008-06-17
MMIC having back-side multi-layer signal routing
App 20070020915 - McCarroll; Christopher P. ;   et al.
2007-01-25
Direct backside interconnect for multiple chip assemblies
Grant 6,175,287 - Lampen , et al. January 16, 2
2001-01-16
Semiconductor structures having dual surface via holes
Grant 5,343,071 - Kazior , et al. August 30, 1
1994-08-30
Selective backside plating of GaAs monolithic microwave integrated circuits
Grant 4,970,578 - Tong , et al. November 13, 1
1990-11-13
Simultaneous formation of via hole and tube structures for GaAs monolithic microwave integrated circuits
Grant 4,927,784 - Kazior , et al. May 22, 1
1990-05-22
Simultaneous formation of via hole and tub structures for GaAs monolithic microwave integrated circuits
Grant 4,807,022 - Kazior , et al. February 21, 1
1989-02-21
Selective backside plating of gaas monolithic microwave integrated circuits
Grant 4,794,093 - Tong , et al. December 27, 1
1988-12-27

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