loadpatents
Patent applications and USPTO patent grants for Kaw; Ravindhar K..The latest application filed is for "integrated circuit with copper interconnect and top level bonding/interconnect layer".
Patent | Date |
---|---|
Integrated circuit incorporating flip chip and wire bonding Grant 7,262,508 - Kelly , et al. August 28, 2 | 2007-08-28 |
Integrated circuit with copper interconnect and top level bonding/interconnect layer Grant 7,202,546 - Salcido, Jr. , et al. April 10, 2 | 2007-04-10 |
Integrated circuit with copper interconnect and top level bonding/interconnect layer App 20050082675 - Salcido, Salvador JR. ;   et al. | 2005-04-21 |
Integrated circuit incorporating flip chip and wire bonding App 20050073054 - Kelly, Michael G. ;   et al. | 2005-04-07 |
Self-aligning infra-red communication link Grant 6,738,583 - Matta , et al. May 18, 2 | 2004-05-18 |
Monolithic semiconductor chip interconnection technique and arrangement Grant 5,021,869 - Kaw June 4, 1 | 1991-06-04 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.