Kaviani; Alireza S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kaviani; Alireza S..The latest application filed is for "active-by-active programmable device".

Company Profile

0.41.5

Kaviani; Alireza S. - San Jose CA
Kaviani; Alireza S. - Toronto Ontario CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Active-by-active programmable device Grant RE49,163 - Kaviani , et al. August 9, 2	2022-08-09
Die-to-die communications scheme Grant 10,498,567 - Kaviani De	2019-12-03
System-level interconnect ring for a programmable integrated circuit Grant 10,042,806 - Kaviani , et al. August 7, 2	2018-08-07
Active-by-active programmable device Grant 10,002,100 - Kaviani , et al. June 19, 2	2018-06-19
Folding duplicate instances of modules in a circuit design Grant 9,875,330 - Ganusov , et al. January 23, 2	2018-01-23
System-level Interconnect Ring For A Programmable Integrated Circuit App 20170220508 - Kaviani; Alireza S. ; et al.	2017-08-03
Active-by-active Programmable Device App 20170220509 - Kaviani; Alireza S. ; et al.	2017-08-03
Folding Duplicate Instances Of Modules In A Circuit Design App 20170161419 - Ganusov; Ilya K. ; et al.	2017-06-08
Lut cascading circuit Grant 9,602,108 - Gaide , et al. March 21, 2	2017-03-21
Data-driven pattern matching in synthesis of circuit designs Grant 8,938,700 - Delaye , et al. January 20, 2	2015-01-20
Programmable integrated circuit and method of asynchronously routing data in a circuit block of an integrated circuit Grant 8,913,601 - Kaviani December 16, 2	2014-12-16
Method of and circuit for generating a spread spectrum clock signal Grant 8,831,064 - Kaviani September 9, 2	2014-09-09
Method and circuit for providing digital frequency synthesis Grant 8,788,553 - Lee , et al. July 22, 2	2014-07-22
Programmable integrated circuit and method of asynchronously routing data in an integrated circuit Grant 8,358,148 - Kaviani January 22, 2	2013-01-22
Integrated circuit and method of asynchronously routing data in an integrated circuit Grant 8,294,490 - Kaviani October 23, 2	2012-10-23
Circuit for digital frequency synthesis in an integrated circuit Grant 7,479,814 - Kaviani , et al. January 20, 2	2009-01-20
Structure for the main oscillator of a counter-controlled delay line Grant 7,477,112 - Pi , et al. January 13, 2	2009-01-13
Method of and circuit for deskewing clock signals in an integrated circuit Grant 7,453,297 - Kaviani November 18, 2	2008-11-18
Method of and circuit for phase shifting a clock signal Grant 7,453,301 - Kaviani November 18, 2	2008-11-18
Circuit for and method of generating a frequency aligned clock signal Grant 7,236,026 - Samad , et al. June 26, 2	2007-06-26
Dual-edge synchronized data sampler Grant 7,190,196 - Kaviani March 13, 2	2007-03-13
Hybrid counter with an asynchronous front end Grant 7,190,756 - Kaviani , et al. March 13, 2	2007-03-13
Counter-controlled delay line Grant 7,071,751 - Kaviani July 4, 2	2006-07-04
Literal sharing method for fast sum-of-products logic Grant 6,978,427 - Kaviani December 20, 2	2005-12-20
Hard phase alignment of clock signals with an oscillator controller Grant 6,943,597 - Kaviani September 13, 2	2005-09-13
Structure for reducing leakage current in submicron IC devices Grant 6,914,449 - Kaviani July 5, 2	2005-07-05
Method and circuit for glitchless clock control Grant 6,873,183 - Kaviani , et al. March 29, 2	2005-03-29
Method and apparatus for reducing jitter and power dissipation in a delay line Grant 6,847,246 - Kaviani , et al. January 25, 2	2005-01-25
DCVSL pulse width controller and system Grant 6,838,919 - Kaviani January 4, 2	2005-01-04
Hard phase alignment of clock signals using asynchronous level-mode state machine Grant 6,838,918 - Kaviani January 4, 2	2005-01-04
FPGA with improved structure for implementing large multiplexers Grant 6,806,732 - Kaviani October 19, 2	2004-10-19
Method and apparatus for reducing jitter in a delay line and a trim unit Grant 6,788,124 - Kaviani September 7, 2	2004-09-07
FPGA with improved structure for implementing large multiplexers Grant 6,784,692 - Kaviani August 31, 2	2004-08-31
Phase detector employing asynchronous level-mode sequential circuitry Grant 6,756,822 - Kaviani June 29, 2	2004-06-29
Literal sharing method for fast sum-of-products logic Grant 6,754,686 - Kaviani June 22, 2	2004-06-22
Configurable logic block for PLD with logic gate for combining output with another configurable logic block Grant 6,603,332 - Kaviani , et al. August 5, 2	2003-08-05
FPGA with improved structure for implementing large multiplexers Grant 6,556,042 - Kaviani April 29, 2	2003-04-29
Configurable logic block for PLD Grant 6,480,023 - Kaviani November 12, 2	2002-11-12
Structure for reducing leakage current in submicron IC devices App 20020141234 - Kaviani, Alireza S.	2002-10-03
Configurable logic block for PLD with logic gate for combining output with another configurable logic block App 20020079921 - Kaviani, Alireza S. ; et al.	2002-06-27
Computational field programmable architecture Grant 6,140,839 - Kaviani , et al. October 31, 2	2000-10-31
Hybrid programmable logic device Grant 5,841,295 - Kaviani November 24, 1	1998-11-24

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