Kaushik; Shiv

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kaushik; Shiv.The latest application filed is for "instruction set architecture-based inter-sequencer communications with a heterogeneous resource".

Company Profile

0.8.11

Kaushik; Shiv - Portland OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Instruction set architecture-based inter-sequencer communications with a heterogeneous resource Grant 9,588,771 - Wang , et al. March 7, 2	2017-03-07
Instruction set architecture-based inter-sequencer communications with a heterogeneous resource Grant 9,459,874 - Wang , et al. October 4, 2	2016-10-04
Instruction Set Architecture-Based Inter-Sequencer Communications With A Heterogeneous Resource App 20150070368 - Wang; Hong ; et al.	2015-03-12
Instruction set architecture-based inter-sequencer communications with a heterogeneous resource Grant 8,914,618 - Wang , et al. December 16, 2	2014-12-16
Instruction Set Architecture-based Inter-sequencer Communications With A Heterogeneous Resource App 20130205122 - WANG; Hong ; et al.	2013-08-08
System and method for selecting optimal processor performance levels by using processor hardware feedback mechanisms Grant 7,917,789 - Fenger , et al. March 29, 2	2011-03-29
Mechanism to emulate user-level multithreading on an OS-sequestered sequencer Grant 7,810,083 - Chinya , et al. October 5, 2	2010-10-05
System And Method For Selecting Optimal Processor Performance Levels By Using Processor Hardware Feedback Mechanisms App 20090089598 - Fenger; Russell J. ; et al.	2009-04-02
Method and apparatus for suspending execution of a thread until a specified memory access occurs Grant 7,363,474 - Rodgers , et al. April 22, 2	2008-04-22
Method and apparatus for suspending execution of a thread until a specified memory access occurs App 20080034190 - Rodgers; Dion ; et al.	2008-02-07
Instruction set architecture-based inter-sequencer communications with a heterogeneous resource App 20070157211 - Wang; Hong ; et al.	2007-07-05
Coherency techniques for suspending execution of a thread until a specified memory access occurs Grant 7,127,561 - Hill , et al. October 24, 2	2006-10-24
Mechanism to emulate user-level multithreading on an OS-sequestered sequencer App 20060150183 - Chinya; Gautham N. ; et al.	2006-07-06
Method and apparatus for suspending execution of a thread until a specified memory access occurs App 20030126186 - Rodgers, Dion ; et al.	2003-07-03
Suspending execution of a thread in a multi-threaded processor App 20030126416 - Marr, Deborah T. ; et al.	2003-07-03
Instruction sequences for suspending execution of a thread until a specified memory access occurs App 20030126379 - Kaushik, Shiv ; et al.	2003-07-03
Coherency techniques for suspending execution of a thread until a specified memory access occurs App 20030126375 - Hill, David L. ; et al.	2003-07-03

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