loadpatents
name:-0.010116100311279
name:-0.020527124404907
name:-0.0068120956420898
Kathail; Vinod K. Patent Filings

Kathail; Vinod K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kathail; Vinod K..The latest application filed is for "hardware-software design flow with high-level synthesis for heterogeneous and programmable devices".

Company Profile
6.20.8
  • Kathail; Vinod K. - Palo Alto CA
  • Kathail; Vinod K. - Cupertino CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Hardware-software Design Flow With High-level Synthesis For Heterogeneous And Programmable Devices
App 20220035607 - Sastry; Akella ;   et al.
2022-02-03
Dataflow graph programming environment for a heterogenous processing system
Grant 11,204,745 - Gupta , et al. December 21, 2
2021-12-21
Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices
Grant 11,188,312 - Sastry , et al. November 30, 2
2021-11-30
Hardware-software design flow for heterogeneous and programmable devices
Grant 10,891,414 - Gupta , et al. January 12, 2
2021-01-12
Compilation flow for a heterogeneous multi-core architecture
Grant 10,860,766 - Sivaraman , et al. December 8, 2
2020-12-08
Hardware-software Design Flow For Heterogeneous And Programmable Devices
App 20200372123 - Gupta; Shail Aditya ;   et al.
2020-11-26
Compilation Flow For A Heterogeneous Multi-core Architecture
App 20200372200 - Sivaraman; Mukund ;   et al.
2020-11-26
Hardware-software Design Flow With High-level Synthesis For Heterogeneous And Programmable Devices
App 20200371759 - Sastry; Akella ;   et al.
2020-11-26
Dataflow Graph Programming Environment For A Heterogenous Processing System
App 20200371761 - Gupta; Shail Aditya ;   et al.
2020-11-26
Hardware and software event tracing for a system-on-chip
Grant 10,635,769 - Skalicky , et al.
2020-04-28
Encapsulating metadata of a platform for application-specific tailoring and reuse of the platform in an integrated circuit
Grant 9,880,966 - Hwang , et al. January 30, 2
2018-01-30
Compilation of system designs
Grant 9,805,152 - Carrillo , et al. October 31, 2
2017-10-31
Automatic implementation of a customized system-on-chip
Grant 9,652,570 - Kathail , et al. May 16, 2
2017-05-16
Compilation of HLL code with hardware accelerated functions
Grant 9,223,921 - Carrillo , et al. December 29, 2
2015-12-29
Hardware and software cosynthesis performance estimation
Grant 9,147,024 - Kathail , et al. September 29, 2
2015-09-29
Automatic generation of a data transfer network
Grant 8,762,916 - Kathail , et al. June 24, 2
2014-06-24
Method and system for the design of pipelines of processors
Grant 7,107,199 - Schreiber , et al. September 12, 2
2006-09-12
Retargetable computer design system
Grant 6,772,106 - Mahlke , et al. August 3, 2
2004-08-03
Method and system for the design of pipelines of processors
App 20040088529 - Schreiber, Robert S. ;   et al.
2004-05-06
Automatic design of VLIW processors
Grant 6,651,222 - Gupta , et al. November 18, 2
2003-11-18
Programmatic synthesis of processor element arrays
Grant 6,507,947 - Schreiber , et al. January 14, 2
2003-01-14
Automatic design of VLIW processors
App 20020133784 - Gupta, Shail Aditya ;   et al.
2002-09-19
Automatic design of VLIW processors
App 20020120914 - Gupta, Shail Aditya ;   et al.
2002-08-29
Automated design of processor systems using feedback from internal measurements of candidate systems
Grant 6,408,428 - Schlansker , et al. June 18, 2
2002-06-18
Auto design of VLIW processors
Grant 6,385,757 - Gupta , et al. May 7, 2
2002-05-07
Method and system for propagating exception status in data registers and for detecting exceptions from speculative operations with non-speculative operations
Grant 5,778,219 - Amerson , et al. July 7, 1
1998-07-07
Method and system for deferring exceptions generated during speculative execution
Grant 5,692,169 - Kathail , et al. November 25, 1
1997-11-25
Cache system for reducing memory latency times
Grant 5,404,484 - Schlansker , et al. April 4, 1
1995-04-04

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