Kashyap; Madhur
Patent Applications and Registrations
Patent applications and USPTO patent grants for Kashyap; Madhur.The latest application filed is for "layout method for integrated circuit including vias".
- Kashyap; Madhur - Noida N/A IN
| Patent | Date |
|---|---|
| Capacitive cell load estimation using electromigration analysis Grant 8,843,873 - Sharma , et al. September 23, 2 | 2014-09-23 |
| Layout Method For Integrated Circuit Including Vias App 20120233575 - KASHYAP; Madhur | 2012-09-13 |
| Method and system for incorporating via redundancy in timing analysis Grant 7,673,268 - Kashyap , et al. March 2, 2 | 2010-03-02 |
| Method And System For Incorporating Via Redundancy In Timing Analysis App 20070256042 - Kashyap; Madhur ; et al. | 2007-11-01 |
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