loadpatents
name:-0.01210880279541
name:-0.013235092163086
name:-0.0009160041809082
Kashyap; Chandramouli V. Patent Filings

Kashyap; Chandramouli V.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kashyap; Chandramouli V..The latest application filed is for "synthesizing current source driver model for analysis of cell characteristics".

Company Profile
0.12.9
  • Kashyap; Chandramouli V. - Round Rock TX
  • Kashyap; Chandramouli V. - Portland OR
  • Kashyap; Chandramouli V. - Austin TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Synthesizing current source driver model for analysis of cell characteristics
Grant 7,761,275 - Chopra , et al. July 20, 2
2010-07-20
Integrated circuit (IC) chip design method, program product and system
Grant 7,552,412 - Abbaspour , et al. June 23, 2
2009-06-23
Methods for computing Miller-factor using coupled peak noise
Grant 7,475,372 - Kashyap , et al. January 6, 2
2009-01-06
Method for estimating propagation noise based on effective capacitance in an integrated circuit chip
Grant 7,346,867 - Su , et al. March 18, 2
2008-03-18
Synthesizing current source driver model for analysis of cell characteristics
App 20070143719 - Chopra; Kaviraj S. ;   et al.
2007-06-21
Methods For Computing Miller-factor Using Coupled Peak Noise
App 20070011630 - Kashyap; Chandramouli V. ;   et al.
2007-01-11
Method for estimating propagation noise based on effective capacitance in an integrated circuit chip
App 20060190881 - Su; Haihua ;   et al.
2006-08-24
Integrated circuit (IC) chip design method, program product and system
App 20060150133 - Abbaspour; Soroush ;   et al.
2006-07-06
Method, apparatus, and program for block-based static timing analysis with uncertainty
Grant 7,000,205 - Devgan , et al. February 14, 2
2006-02-14
Method and system for determining an interconnect delay utilizing an effective capacitance metric (ECM) signal delay model
Grant 6,968,306 - Alpert , et al. November 22, 2
2005-11-22
Interconnect delay and slew metrics based on the lognormal distribution
Grant 6,950,996 - Alpert , et al. September 27, 2
2005-09-27
Apparatus and method for incorporating driver sizing into buffer insertion using a delay penalty estimation technique
Grant 6,915,496 - Alpert , et al. July 5, 2
2005-07-05
Method and system for extending delay and slew metrics to ramp inputs
Grant 6,868,533 - Alpert , et al. March 15, 2
2005-03-15
Method, apparatus, and program for block-based static timing analysis with uncertainty
App 20040243954 - Devgan, Anirudh ;   et al.
2004-12-02
Interconnect delay and slew metrics based on the lognormal distribution
App 20040243955 - Alpert, Charles Jay ;   et al.
2004-12-02
Robust delay metric for RC circuits
Grant 6,807,659 - Alpert , et al. October 19, 2
2004-10-19
Method and system for extending delay and slew metrics to ramp inputs
App 20040103379 - Alpert, Charles Jay ;   et al.
2004-05-27
Apparatus and method for incorporating driver sizing into buffer insertion using a delay penalty estimation technique
App 20040064793 - Alpert, Charles Jay ;   et al.
2004-04-01
Robust delay metric for RC circuits
App 20040064798 - Alpert, Charles Jay ;   et al.
2004-04-01
Method for handling coupling effects in static timing analysis
Grant 6,615,395 - Hathaway , et al. September 2, 2
2003-09-02
Driving point model utilizing a realizable reduced order circuit for determining a delay of a gate driving an interconnect with inductance
Grant 6,496,960 - Kashyap , et al. December 17, 2
2002-12-17

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed