Kashimura; Masahiko
Patent Applications and Registrations
Patent applications and USPTO patent grants for Kashimura; Masahiko.The latest application filed is for "booster circuit".
- Kashimura; Masahiko - Kawasaki JP
- Kashimura; Masahiko - Kanagawa JP
- Kashimura; Masahiko - Tokyo JP
| Patent | Date |
|---|---|
| Booster circuit Grant 8,106,703 - Nagai , et al. January 31, 2 | 2012-01-31 |
| Nonvolatile semiconductor memory device Grant 8,004,902 - Amanai , et al. August 23, 2 | 2011-08-23 |
| Nonvolatile semiconductor memory, and method for reading data Grant 7,924,612 - Kashimura April 12, 2 | 2011-04-12 |
| Booster Circuit App 20100301927 - NAGAI; Yoshihiro ; et al. | 2010-12-02 |
| Nonvolatile Semiconductor Memory Device App 20100124125 - AMANAI; Masakazu ; et al. | 2010-05-20 |
| Nonvolatile semiconductor memory, and method for reading data App 20100118609 - Kashimura; Masahiko | 2010-05-13 |
| Non-volatile memory device and inspection method for non-volatile memory device Grant 7,385,856 - Oga , et al. June 10, 2 | 2008-06-10 |
| Nonvolatile Semiconductor Memory Device With Trench Structure App 20070187746 - KASHIMURA; Masahiko | 2007-08-16 |
| Non-volatile memory device and inspection method for non-volatile memory device App 20050213418 - Oga, Hirofumi ; et al. | 2005-09-29 |
| Non-volatile semiconductor memory device Grant 6,141,250 - Kashimura October 31, 2 | 2000-10-31 |
| Decoder buffer circuit incorporated in semiconductor memory device Grant 4,953,133 - Kashimura August 28, 1 | 1990-08-28 |
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