Karve; Gauri V.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Karve; Gauri V..The latest application filed is for "epitaxially grown silicon germanium channel finfet with silicon underlayer".

Company Profile

0.13.9

Karve; Gauri V. - Cohoes NY
Karve; Gauri V. - Austin TX
Karve; Gauri V. - Fishkill NY US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Epitaxially Grown Silicon Germanium Channel Finfet With Silicon Underlayer App 20160163707 - Cheng; Kangguo ; et al.	2016-06-09
Semiconductor devices with different dielectric thicknesses Grant 9,362,280 - Karve , et al. June 7, 2	2016-06-07
Dual high-K oxides with SiGe channel Grant RE45,955 - Luo , et al. March 29, 2	2016-03-29
Epitaxially grown silicon germanium channel FinFET with silicon underlayer Grant 9,287,264 - Cheng , et al. March 15, 2	2016-03-15
Semiconductor Devices With Different Dielectric Thicknesses App 20130249015 - Karve; Gauri V. ; et al.	2013-09-26
Semiconductor devices with different dielectric thicknesses Grant 8,460,996 - Karve , et al. June 11, 2	2013-06-11
Dual high-k oxides with sige channel Grant 8,017,469 - Luo , et al. September 13, 2	2011-09-13
Dual substrate orientation or bulk on SOI integrations using oxidation for silicon epitaxy spacer formation Grant 7,790,528 - Spencer , et al. September 7, 2	2010-09-07
Dual High-k Oxides With Sige Channel App 20100184260 - Luo; Tien-Ying ; et al.	2010-07-22
Step height reduction between SOI and EPI for DSO and BOS integration Grant 7,749,829 - Karve , et al. July 6, 2	2010-07-06
Dual gate oxide device integration Grant 7,709,331 - Karve , et al. May 4, 2	2010-05-04
Method for forming a dual metal gate structure Grant 7,666,730 - Karve , et al. February 23, 2	2010-02-23
Semiconductor Devices With Different Dielectric Thicknesses App 20090108296 - Karve; Gauri V. ; et al.	2009-04-30
Dual Gate Oxide Device Integration App 20090068807 - Karve; Gauri V. ; et al.	2009-03-12
Method For Forming A Dual Metal Gate Structure App 20090004792 - Karve; Gauri V. ; et al.	2009-01-01
Dual substrate orientation or bulk on SOI integrations using oxidation for silicon epitaxy spacer formation App 20080274595 - Spencer; Gregory S. ; et al.	2008-11-06
Step height reduction between SOI and EPI for DSO and BOS integration App 20080274594 - Karve; Gauri V. ; et al.	2008-11-06
Method for forming a dual metal gate structure Grant 7,445,981 - Karve , et al. November 4, 2	2008-11-04

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.