Karthikeyan; Subramanian

Patent Applications and Registrations

Patent applications and USPTO patent grants for Karthikeyan; Subramanian.The latest application filed is for "semiconductor test device with heating circuit".

Company Profile

0.6.9

Karthikeyan; Subramanian - Schnecksville PA
Karthikeyan; Subramanian - Orlando FL

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor test device with heating circuit Grant 7,804,291 - Kang , et al. September 28, 2	2010-09-28
Test semiconductor device and method for determining Joule heating effects in such a device Grant 7,388,395 - Kang , et al. June 17, 2	2008-06-17
Semiconductor device having reduced intra-level and inter-level capacitance Grant 7,301,107 - Karthikeyan , et al. November 27, 2	2007-11-27
Semiconductor Test Device With Heating Circuit App 20070168818 - Kang; Seung H. ; et al.	2007-07-19
Test semiconductor device and method for determining Joule heating effects in such a device App 20060192584 - Kang; Seung H. ; et al.	2006-08-31
Mask layer and dual damascene interconnect structure in a semiconductor device Grant 7,067,419 - Huang , et al. June 27, 2	2006-06-27
Test semiconductor device and method for determining Joule heating effects in such a device Grant 7,061,264 - Kang , et al. June 13, 2	2006-06-13
Semiconductor test device with heating circuit App 20060066335 - Kang; Seung H. ; et al.	2006-03-30
Test semiconductor device and method for determining Joule heating effects in such a device App 20060066337 - Kang; Seung H. ; et al.	2006-03-30
Method to avoid copper contamination of a via or dual damascene structure Grant 7,005,375 - Karthikeyan , et al. February 28, 2	2006-02-28
Mask layer and dual damascene interconnect structure in a semiconductor device App 20040121579 - Huang, Robert YS ; et al.	2004-06-24
Method and structure of a reducing intra-level and inter-level capacitance of a semiconductor device App 20040084761 - Karthikeyan, Subramanian ; et al.	2004-05-06
Method to avoid copper contamination of a via or dual damascene structure App 20040063307 - Karthikeyan, Subramanian ; et al.	2004-04-01
Method and structure of a reducing intra-level and inter-level capacitance of a semiconductor device App 20030213617 - Karthikeyan, Subramanian ; et al.	2003-11-20
Mask layer and dual damascene interconnect structure in a semiconductor device App 20030119305 - Huang, Robert Y. S. ; et al.	2003-06-26

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