Karp; James

Patent Applications and Registrations

Patent applications and USPTO patent grants for Karp; James.The latest application filed is for "integrated circuit device with electrostatic discharge (esd) protection".

Company Profile

7.72.24

Karp; James - Saratoga CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Electrostatic discharge (ESD) protection in stacked chips Grant 11,398,469 - Karp July 26, 2	2022-07-26
Electro-static discharge (ESD) damage self-test Grant 11,177,654 - Jennings , et al. November 16, 2	2021-11-16
Integrated circuit device with electrostatic discharge (ESD) protection Grant 11,114,429 - Karp September 7, 2	2021-09-07
Method and apparatus of package enabled ESD protection Grant 11,043,484 - Shi , et al. June 22, 2	2021-06-22
Method and apparatus for electronics-harmful-radiation (EHR) measurement and monitoring Grant 10,901,097 - Karp , et al. January 26, 2	2021-01-26
Single event latch-up (SEL) mitigation techniques Grant 10,861,848 - Hart , et al. December 8, 2	2020-12-08
Integrated Circuit Device With Electrostatic Discharge (esd) Protection App 20200343237 - Karp; James	2020-10-29
Single event latch-up (SEL) mitigation techniques Grant 10,811,493 - Karp , et al. October 20, 2	2020-10-20
Mitigation for FinFET technology using deep isolation Grant 10,636,869 - Karp , et al.	2020-04-28
Single Event Latch-up (sel) Mitigation Techniques App 20200066837 - Karp; James ; et al.	2020-02-27
Single Event Latch-up (sel) Mitigation Techniques App 20200066713 - Hart; Michael J. ; et al.	2020-02-27
Integrated circuit device and method of transmitting data in an integrated circuit device Grant 10,522,531 - Karp Dec	2019-12-31
ESD protection in a stacked integrated circuit assembly Grant 10,497,677 - Karp De	2019-12-03
Mitigation For Finfet Technology Using Deep Isolation App 20190280086 - Karp; James ; et al.	2019-09-12
Circuit for increasing the impedance of an ESD path in an input/output circuit and method of implementing the same Grant 10,325,901 - Fakhruddin , et al.	2019-06-18
Configurable single event latch-up (SEL) and electrical overvoltage stress (EOS) detection circuit Grant 10,289,178 - Lynam , et al.	2019-05-14
Removal of electrostatic charges from an interposer via a ground pad thereof for die attach for formation of a stacked die Grant 10,015,916 - Karp July 3, 2	2018-07-03
Removal of electrostatic charges from interposer for die attachment Grant 9,960,227 - Hart , et al. May 1, 2	2018-05-01
Wafer to wafer stacking Grant 9,831,218 - Karp , et al. November 28, 2	2017-11-28
Method and circuits for communication in multi-die packages Grant 9,607,948 - Karp , et al. March 28, 2	2017-03-28
On chip detection of electrical overstress events Grant 9,575,111 - Karp , et al. February 21, 2	2017-02-21
High voltage RC-clamp for electrostatic discharge (ESD) protection Grant 9,548,738 - Karp January 17, 2	2017-01-17
Circuit design-specific failure in time rate for single event upsets Grant 9,483,599 - Jain , et al. November 1, 2	2016-11-01
Selection of logic paths for redundancy Grant 9,484,919 - Jain , et al. November 1, 2	2016-11-01
Method And Circuits For Communication In Multi-die Packages App 20160293548 - Karp; James ; et al.	2016-10-06
Circuits for and methods of providing a charge device model ground path using substrate taps in an integrated circuit device Grant 9,462,674 - Fakhruddin , et al. October 4, 2	2016-10-04
Inductive structure formed using through silicon vias Grant 9,406,738 - Kireev , et al. August 2, 2	2016-08-02
Integrated circuit having improved radiation immunity Grant 9,379,109 - Karp , et al. June 28, 2	2016-06-28
Preparing layouts for semiconductor circuits Grant 9,378,322 - Karp June 28, 2	2016-06-28
Programmable integrated circuit having different types of configuration memory Grant 9,275,180 - Karp March 1, 2	2016-03-01
Integrated circuit having improved radiation immunity Grant 9,236,353 - Jain , et al. January 12, 2	2016-01-12
Integrated circuit having improved radiation immunity Grant 9,058,853 - Hart , et al. June 16, 2	2015-06-16
Method and apparatus to reduce power segmentation overhead within an integrated circuit Grant 9,058,454 - Young , et al. June 16, 2	2015-06-16
High voltage RC-clamp for electrostatic discharge (ESD) protection Grant 9,013,845 - Karp April 21, 2	2015-04-21
Circuit for and method of enabling the discharge of electric charge in an integrated circuit Grant 9,013,844 - Karp April 21, 2	2015-04-21
Reduction of single event upsets within a semiconductor integrated circuit Grant 9,000,529 - Jain , et al. April 7, 2	2015-04-07
Electro-static discharge protection for die of a multi-chip module Grant 8,982,581 - Karp , et al. March 17, 2	2015-03-17
Memory array having improved radiation immunity Grant 8,981,491 - Hart , et al. March 17, 2	2015-03-17
Removal Of Electrostatic Charges From Interposer For Die Attachment App 20150069577 - Hart; Michael J. ; et al.	2015-03-12
Enhanced immunity from electrostatic discharge Grant 8,947,839 - Karp February 3, 2	2015-02-03
Cell-level electrostatic discharge protection for an integrated circuit Grant 8,881,085 - Karp , et al. November 4, 2	2014-11-04
Semiconductor structure for an electrostatic discharge protection circuit Grant 8,866,229 - Fakhruddin , et al. October 21, 2	2014-10-21
Interposer having an inductor Grant 8,823,133 - Jenkins , et al. September 2, 2	2014-09-02
Circuit For And Method Of Enabling The Discharge Of Electric Charge In An Integrated Circuit App 20140198416 - Karp; James	2014-07-17
Integrated Circuit Having Improved Radiation Immunity App 20140145293 - Jain; Praful ; et al.	2014-05-29
Integrated Circuit Having Improved Radiation Immunity App 20140048887 - Hart; Michael J. ; et al.	2014-02-20
Operating a programmable integrated circuit with functionally equivalent configuration bitstreams Grant 8,519,741 - Karp , et al. August 27, 2	2013-08-27
High Voltage Rc-clamp For Electrostatic Discharge (esd) Protection App 20130215541 - Karp; James	2013-08-22
T-coil network design for improved bandwidth and electrostatic discharge immunity Grant 8,453,092 - Kireev , et al. May 28, 2	2013-05-28
Inductive Structure Formed Using Through Silicon Vias App 20130020675 - Kireev; Vassili ; et al.	2013-01-24
Hybrid integrated circuit device Grant 8,293,547 - Karp , et al. October 23, 2	2012-10-23
Interposer Having An Inductor App 20120248569 - Jenkins; Michael O. ; et al.	2012-10-04
T-coil Network Design For Improved Bandwidth And Electrostatic Discharge Immunity App 20120188671 - Kireev; Vassili ; et al.	2012-07-26
Shared electrostatic discharge protection for integrated circuit output drivers Grant 8,218,277 - Li , et al. July 10, 2	2012-07-10
T-coil network design for improved bandwidth and electrostatic discharge immunity Grant 8,181,140 - Kireev , et al. May 15, 2	2012-05-15
Integrated circuit device with low capacitance and high thermal conductivity interface Grant 8,174,112 - Karp , et al. May 8, 2	2012-05-08
Method and apparatus to reduce footprint of ESD protection within an integrated circuit Grant 8,134,813 - Karp , et al. March 13, 2	2012-03-13
Electro-static Discharge Protection For Die Of A Multi-chip Module App 20120002392 - Karp; James ; et al.	2012-01-05
Method and apparatus for evaluating paths in an integrated circuit design Grant 8,079,002 - Lo , et al. December 13, 2	2011-12-13
Hybrid Integrated Circuit Device App 20110147949 - Karp; James ; et al.	2011-06-23
Non-volatile memory cell with charge storage element and method of programming Grant 7,947,980 - Toutounchi , et al. May 24, 2	2011-05-24
T-coil Network Design For Improved Bandwidth And Electrostatic Discharge Immunity App 20110113401 - Kireev; Vassili ; et al.	2011-05-12
Formation of a hybrid integrated circuit device Grant 7,919,845 - Karp , et al. April 5, 2	2011-04-05
Shared Electrostatic Discharge Protection For Integrated Circuit Output Drivers App 20110058290 - Li; Richard C. ; et al.	2011-03-10
Enhanced Immunity From Electrostatic Discharge App 20110026173 - Karp; James	2011-02-03
Common centroid electrostatic discharge protection for integrated circuit devices Grant 7,812,674 - Karp October 12, 2	2010-10-12
Pass gate with improved latchup immunity Grant 7,812,642 - Jennings , et al. October 12, 2	2010-10-12
Method And Apparatus To Reduce Footprint Of Esd Protection Within An Integrated Circuit App 20100188787 - Karp; James ; et al.	2010-07-29
Common Centroid Electrostatic Discharge Protection for Integrated Circuit Devices App 20100127782 - Karp; James	2010-05-27
Three-terminal non-volatile memory element with hybrid gate dielectric Grant 7,687,797 - Karp , et al. March 30, 2	2010-03-30
Formation of a hybrid integrated circuit device App 20090160482 - Karp; James ; et al.	2009-06-25
Non-volatile memory cell with charge storage element and method of programming Grant 7,544,968 - Toutounchi , et al. June 9, 2	2009-06-09
PMOS three-terminal non-volatile memory element and method of programming Grant 7,450,431 - Karp , et al. November 11, 2	2008-11-11
Method of programming a three-terminal non-volatile memory element using source-drain bias Grant 7,420,842 - Ahrens , et al. September 2, 2	2008-09-02
Electrical fuse for integrated circuits Grant 7,002,219 - de Jong , et al. February 21, 2	2006-02-21
Ballast resistor with reduced area for ESD protection Grant 6,740,936 - Gitlin , et al. May 25, 2	2004-05-25
Structure and method for preventing barrier failure Grant 6,638,852 - Karp October 28, 2	2003-10-28
Non-volatile memory array using gate breakdown structures Grant 6,522,582 - Rao , et al. February 18, 2	2003-02-18
Three terminal non-volatile memory element Grant 6,266,269 - Karp , et al. July 24, 2	2001-07-24
Non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process Grant 6,044,012 - Rao , et al. March 28, 2	2000-03-28

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.