Karchmer; David

Patent Applications and Registrations

Patent applications and USPTO patent grants for Karchmer; David.The latest application filed is for "methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits".

Company Profile

0.28.4

Karchmer; David - Los Altos CA US
Karchmer; David - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
M/A for performing incremental compilation using top-down and bottom-up design approaches Grant 8,589,838 - Borer , et al. November 19, 2	2013-11-19
Method and apparatus for performing path-level skew optimization and analysis for a logic design Grant 8,572,530 - Fung , et al. October 29, 2	2013-10-29
Method for adding device information by extending an application programming interface Grant 8,516,504 - Park , et al. August 20, 2	2013-08-20
Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches Grant 8,250,505 - Borer , et al. August 21, 2	2012-08-21
Method and apparatus for comparing programmable logic device configurations Grant 8,161,469 - Iotov , et al. April 17, 2	2012-04-17
Early timing estimation of timing statistical properties of placement Grant 8,112,728 - Hutton , et al. February 7, 2	2012-02-07
Method and apparatus for compiling programmable logic device configurations Grant 8,001,537 - Iotov , et al. August 16, 2	2011-08-16
Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits Grant 7,877,721 - Schleicher, II , et al. January 25, 2	2011-01-25
Method and apparatus for performing path-level skew optimization and analysis for a logic design Grant 7,853,911 - Fung , et al. December 14, 2	2010-12-14
Performance visualization system Grant 7,784,008 - Hutton , et al. August 24, 2	2010-08-24
Method and apparatus for performing parallel slack computation Grant 7,725,856 - Govig , et al. May 25, 2	2010-05-25
Method and apparatus for performing incremental compilation using top-down and bottom-up design approaches Grant 7,669,157 - Borer , et al. February 23, 2	2010-02-23
User-directed timing-driven synthesis Grant 7,587,688 - Van Antwerpen , et al. September 8, 2	2009-09-08
Clock domain conflict analysis for timing graphs Grant 7,584,443 - Govig , et al. September 1, 2	2009-09-01
Early timing estimation of timing statistical properties of placement Grant 7,577,929 - Hutton , et al. August 18, 2	2009-08-18
Method and apparatus for performing incremental compilation Grant 7,464,362 - Borer , et al. December 9, 2	2008-12-09
Mask-programmable logic device with programmable portions Grant 7,358,766 - Lawson , et al. April 15, 2	2008-04-15
Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits App 20070294659 - Schleicher; James G. II ; et al.	2007-12-20
Methods for producing equivalent field-programmable gate arrays and structured application specific integrated circuits Grant 7,275,232 - Schleicher, II , et al. September 25, 2	2007-09-25
Using assignment decision diagrams with control nodes for sequential review during behavioral simulation Grant 7,231,337 - Karchmer , et al. June 12, 2	2007-06-12
Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits App 20060225008 - Schleicher; James G. II ; et al.	2006-10-05
Mask-programmable logic device with programmable portions App 20060197552 - Lawson; Jimmy ; et al.	2006-09-07
Mask-programmable logic device with programmable portions Grant 7,064,580 - Lawson , et al. June 20, 2	2006-06-20
Mask-programmable logic device with programmable portions App 20060017458 - Lawson; Jimmy ; et al.	2006-01-26
Behaviorial digital simulation using hybrid control and data flow representations Grant 6,961,690 - Karchmer , et al. November 1, 2	2005-11-01
Using assignment decision diagrams with control nodes for sequential review during behavioral simulation Grant 6,697,773 - Karchmer , et al. February 24, 2	2004-02-24
Programmable logic array device design using parameterized logic modules Grant 6,173,245 - Karchmer , et al. January 9, 2	2001-01-09
Methods and apparatus for automatically generating interconnect patterns in programmable logic devices Grant 6,167,364 - Stellenberg , et al. December 26, 2	2000-12-26
Local compilation in context within a design hierarchy Grant 6,026,226 - Heile , et al. February 15, 2	2000-02-15

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