Kapur; Rohit

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kapur; Rohit.The latest application filed is for "mapping physical shift failures to scan cells for detecting physical faults in integrated circuits".

Company Profile

2.45.33

Kapur; Rohit - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Layout-aware test pattern generation and fault detection Grant 11,237,210 - Sanyal , et al. February 1, 2	2022-02-01
Automatically generated schematics and visualization Grant 10,621,298 - Chandra , et al.	2020-04-14
Mapping physical shift failures to scan cells for detecting physical faults in integrated circuits Grant 10,605,863 - Kundu , et al.	2020-03-31
Command coverage analyzer Grant 10,445,225 - Gopalakrishnan , et al. Oc	2019-10-15
Layout-aware test pattern generation and fault detection Grant 10,254,343 - Sanyal , et al.	2019-04-09
Scheme for masking output of scan chains in test circuit Grant 10,203,370 - Saikia , et al. Feb	2019-02-12
Mapping Physical Shift Failures To Scan Cells For Detecting Physical Faults In Integrated Circuits App 20180267098 - Kundu; Subhadip ; et al.	2018-09-20
Handling of undesirable distribution of unknown values in testing of circuit using automated test equipment Grant 10,067,187 - Chandra , et al. September 4, 2	2018-09-04
Command Coverage Analyzer App 20180107587 - Gopalakrishnan; Chandramouli ; et al.	2018-04-19
Scheme for Masking Output of Scan Chains in Test Circuit App 20170131354 - Saikia; Jyotirmoy ; et al.	2017-05-11
Automatically Generated Schematics And Visualization App 20170116364 - Chandra; Anshuman ; et al.	2017-04-27
Scheme for masking output of scan chains in test circuit Grant 9,588,179 - Saikia , et al. March 7, 2	2017-03-07
Identifying Failure Indicating Scan Test Cells Of A Circuit-under-test App 20170059651 - Kundu; Subhadip ; et al.	2017-03-02
Identifying failure indicating scan test cells of a circuit-under-test Grant 9,568,550 - Kundu , et al. February 14, 2	2017-02-14
Scheme for Masking Output of Scan Chains in Test Circuit App 20160341795 - Chandra; Anshuman ; et al.	2016-11-24
Scheme for masking output of scan chains in test circuit Grant 9,417,287 - Chandra , et al. August 16, 2	2016-08-16
Reordering or removal of test patterns for detecting faults in integrated circuit Grant 9,411,014 - Podder , et al. August 9, 2	2016-08-09
Command coverage analyzer Grant 9,342,439 - Gopalakrishnan , et al. May 17, 2	2016-05-17
Localizing fault flop in circuit by using modified test pattern Grant 9,329,235 - Bhattacharya , et al. May 3, 2	2016-05-03
Hierarchical testing architecture using core circuit with pseudo-interfaces Grant 9,239,897 - Chebiyam , et al. January 19, 2	2016-01-19
Command Coverage Analyzer App 20150363295 - Gopalakrishnan; Chandramouli ; et al.	2015-12-17
Test design optimizer for configurable scan architectures Grant 8,954,918 - Kapur , et al. February 10, 2	2015-02-10
Handling of Undesirable Distribution of Unknown Values in Testing of Circuit Using Automated Test Equipment App 20150025819 - Chandra; Anshuman ; et al.	2015-01-22
Scheme for Masking Output of Scan Chains in Test Circuit App 20140372822 - Saikia; Jyotirmoy ; et al.	2014-12-18
Scheme for Masking Output of Scan Chains in Test Circuit App 20140317463 - Chandra; Anshuman ; et al.	2014-10-23
Hierarchical Testing Architecture Using Core Circuit with Pseudo-Interfaces App 20140304672 - Chebiyam; Subramanian B. ; et al.	2014-10-09
Reordering or Removal of Test Patterns for Detecting Faults in Integrated Circuit App 20140289579 - Podder; Sushovan ; et al.	2014-09-25
Localizing Fault Flop in Circuit by Using Modified Test Pattern App 20140281777 - Bhattacharya; Parthajit ; et al.	2014-09-18
Test Design Optimizer For Configurable Scan Architectures App 20140059399 - Kapur; Rohit ; et al.	2014-02-27
Systemic diagnostics for increasing wafer yield Grant 8,660,818 - Kapur , et al. February 25, 2	2014-02-25
Layout-aware Test Pattern Generation And Fault Detection App 20140032156 - Sanyal; Alodeep ; et al.	2014-01-30
Test design optimizer for configurable scan architectures Grant 8,584,073 - Kapur , et al. November 12, 2	2013-11-12
Accelerating automatic test pattern generation in a multi-core computing environment via speculatively scheduled sequential multi-level parameter value optimization Grant 8,521,464 - Kumar , et al. August 27, 2	2013-08-27
Test architecture including cyclical cache chains, selective bypass scan chain segments, and blocking circuitry Grant 8,479,067 - Chandra , et al. July 2, 2	2013-07-02
Accelerating Automatic Test Pattern Generation in a Multi-Core Computing Environment via Speculatively Scheduled Sequential Multi-Level Parameter Value Optimization App 20110301907 - Kumar; Ashwin ; et al.	2011-12-08
Implementing hierarchical design-for-test logic for modular circuit design Grant 8,065,651 - Kapur , et al. November 22, 2	2011-11-22
Test Architecture Including Cyclical Cache Chains, Selective Bypass Scan Chain Segments, And Blocking Circuitry App 20110258498 - Chandra; Anshuman ; et al.	2011-10-20
Dynamically reconfigurable shared scan-in test architecture Grant 7,900,105 - Kapur , et al. March 1, 2	2011-03-01
Systemic Diagnostics For Increasing Wafer Yield App 20110040528 - Kapur; Rohit ; et al.	2011-02-17
Dynamically reconfigurable shared scan-in test architecture Grant 7,836,368 - Kapur , et al. November 16, 2	2010-11-16
Dynamically reconfigurable shared scan-in test architecture Grant 7,836,367 - Kapur , et al. November 16, 2	2010-11-16
Scan compression circuit and method of design therefor Grant 7,814,444 - Wohl , et al. October 12, 2	2010-10-12
Slack-based transition-fault testing Grant 7,797,601 - Kapur , et al. September 14, 2	2010-09-14
Dynamically Reconfigurable Shared Scan-In Test Architecture App 20100223516 - Kapur; Rohit ; et al.	2010-09-02
Dynamically reconfigurable shared scan-in test architecture Grant 7,774,663 - Kapur , et al. August 10, 2	2010-08-10
Method And Apparatus For Implementing A Hierarchical Design-for-test Solution App 20100192030 - Kapur; Rohit ; et al.	2010-07-29
Dynamically reconfigurable shared scan-in test architecture Grant 7,743,299 - Kapur , et al. June 22, 2	2010-06-22
Method and apparatus for limiting power dissipation in test Grant 7,669,098 - Kapur , et al. February 23, 2	2010-02-23
Dynamically Reconfigurable Shared Scan-In Test Architecture App 20100031101 - Kapur; Rohit ; et al.	2010-02-04
Test Design Optimizer For Configurable Scan Architectures App 20100017760 - Kapur; Rohit ; et al.	2010-01-21
Dynamically Reconfigurable Shared Scan-In Test Architecture App 20090313514 - Kapur; Rohit ; et al.	2009-12-17
Dynamically Reconfigurable Shared Scan-In Test Architecture App 20090271673 - Kapur; Rohit ; et al.	2009-10-29
Dynamically reconfigurable shared scan-in test architecture Grant 7,596,733 - Kapur , et al. September 29, 2	2009-09-29
Slack-based Transition-fault Testing App 20090235133 - Kapur; Rohit ; et al.	2009-09-17
Slack-based transition-fault testing Grant 7,546,500 - Kapur , et al. June 9, 2	2009-06-09
Dynamically Reconfigurable Shared Scan-In Test Architecture App 20080301510 - Kapur; Rohit ; et al.	2008-12-04
Dynamically Reconfigurable Shared Scan-In Test Architecture App 20080294955 - Kapur; Rohit ; et al.	2008-11-27
Scan compression circuit and method of design therefor App 20080256497 - Wohl; Peter ; et al.	2008-10-16
Dynamically reconfigurable shared scan-in test architecture Grant 7,418,640 - Kapur , et al. August 26, 2	2008-08-26
Method and apparatus for limiting power dissipation in test App 20080141188 - Kapur; Rohit ; et al.	2008-06-12
Slack-based transition-fault testing App 20070206354 - Kapur; Rohit ; et al.	2007-09-06
Deterministic bist architecture including MISR filter Grant 6,993,694 - Kapur , et al. January 31, 2	2006-01-31
System and method for automatically retargeting test vectors between different tester types Grant 6,990,619 - Kapur , et al. January 24, 2	2006-01-24
Dynamically reconfigurable shared scan-in test architecture App 20050268190 - Kapur, Rohit ; et al.	2005-12-01
System and method for time slicing deterministic patterns for reseeding in logic built-in self-test Grant 6,807,646 - Williams , et al. October 19, 2	2004-10-19
System and method for high-level test planning for layout Grant 6,766,501 - Duggirala , et al. July 20, 2	2004-07-20
Method and system for performing deterministic analysis and speculative analysis for more efficient automatic test pattern generation Grant 6,631,344 - Kapur , et al. October 7, 2	2003-10-07
Dynamic scan chains and test pattern generation methodologies therefor Grant 6,615,380 - Kapur , et al. September 2, 2	2003-09-02
System and method for high-level test planning for layout Grant 6,434,733 - Duggirala , et al. August 13, 2	2002-08-13
Intelligent test vector formatting to reduce test vector size and allow encryption thereof for integrated circuit testing App 20020093356 - Williams, Thomas W. ; et al.	2002-07-18
Method for placement-based scan-in and scan-out ports selection Grant 6,405,355 - Duggirala , et al. June 11, 2	2002-06-11
Method and system for controlling test data volume in deterministic test pattern generation Grant 6,385,750 - Kapur , et al. May 7, 2	2002-05-07

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