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Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator
Grant 11,093,674 - Asaad , et al. August 17, 2 | 2021-08-17 |
Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator
Grant 11,047,907 - Asaad , et al. June 29, 2 | 2021-06-29 |
Transmit And Receive Radio Frequency (rf) Signals Without The Use Of Baseband Generators And Local Oscillators For Up Conversion And Down Conversion
App 20210067256 - Kapur; Mohit ; et al. | 2021-03-04 |
Transmit and receive radio frequency (RF) signals without the use of baseband generators and local oscillators for up conversion and down conversion
Grant 10,924,193 - Kapur , et al. February 16, 2 | 2021-02-16 |
Secure processing environment for protecting sensitive information
Grant 10,904,226 - Boivie , et al. January 26, 2 | 2021-01-26 |
Phase Continuous Signal Generation Using Direct Digital Synthesis
App 20200272196 - Kapur; Mohit ; et al. | 2020-08-27 |
System And Method For Supporting Secure Objects Using A Memory Access Control Monitor
App 20200218799 - Boivie; Richard Harold ; et al. | 2020-07-09 |
Phase continuous signal generation using direct digital synthesis
Grant 10,705,556 - Kapur , et al. | 2020-07-07 |
System and method for supporting secure objects using a memory access control monitor
Grant 10,628,579 - Boivie , et al. | 2020-04-21 |
Secure Processing Environment For Protecting Sensitive Information
App 20200092267 - Boivie; Richard H. ; et al. | 2020-03-19 |
Cycle Accurate And Cycle Reproducible Memory For An Fpga Based Hardware Accelerator
App 20200049764 - Asaad; Sameh W. ; et al. | 2020-02-13 |
Secure processing environment for protecting sensitive information
Grant 10,547,596 - Boivie , et al. Ja | 2020-01-28 |
Secure processing environment for protecting sensitive information
Grant 10,523,640 - Boivie , et al. Dec | 2019-12-31 |
Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator
Grant 10,488,460 - Asaad , et al. Nov | 2019-11-26 |
Secure Processing Environment For Protecting Sensitive Information
App 20190230069 - Boivie; Richard H. ; et al. | 2019-07-25 |
Secure processing environment for protecting sensitive information
Grant 10,298,545 - Boivie , et al. | 2019-05-21 |
Generating Clock Signals For A Cycle Accurate, Cycle Reproducible Fpga Based Hardware Accelerator
App 20190147130 - Asaad; Sameh W. ; et al. | 2019-05-16 |
Secure Processing Environment For Protecting Sensitive Information
App 20190116164 - Boivie; Richard H. ; et al. | 2019-04-18 |
Transmit And Receive Radio Frequency (rf) Signals Without The Use Of Baseband Generators And Local Oscillators For Up Conversion And Down Conversion
App 20190103927 - Kapur; Mohit ; et al. | 2019-04-04 |
Phase Continuous Signal Generation Using Direct Digital Synthesis
App 20190101950 - Kapur; Mohit ; et al. | 2019-04-04 |
Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator
Grant 10,176,281 - Asaad , et al. J | 2019-01-08 |
Secure processing environment for protecting sensitive information
Grant 10,158,607 - Boivie , et al. Dec | 2018-12-18 |
Cycle Accurate And Cycle Reproducible Memory For An Fpga Based Hardware Accelerator
App 20160169970 - Asaad; Sameh W. ; et al. | 2016-06-16 |
System And Method For Supporting Secure Objects Using A Memory Access Control Monitor
App 20160171250 - Boivie; Richard Harold ; et al. | 2016-06-16 |
Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator
Grant 9,286,423 - Asaad , et al. March 15, 2 | 2016-03-15 |
Generating Clock Signals For A Cycle Accurate, Cycle Reproducible Fpga Based Hardware Accelerator
App 20160063155 - Asaad; Sameh W. ; et al. | 2016-03-03 |
Secure Processing Environment For Protecting Sensitive Information
App 20160006703 - Boivie; Richard H. ; et al. | 2016-01-07 |
Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator
Grant 9,230,046 - Asaad , et al. January 5, 2 | 2016-01-05 |
Wire like link for cycle reproducible and cycle accurate hardware accelerator
Grant 9,002,693 - Asaad , et al. April 7, 2 | 2015-04-07 |
Secure Processing Environment For Protecting Sensitive Information
App 20150074392 - Boivie; Richard H. ; et al. | 2015-03-12 |
Increasing throughput of multiplexed electrical bus in pipe-lined architecture
Grant 8,737,233 - Asaad , et al. May 27, 2 | 2014-05-27 |
Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)
Grant 8,640,070 - Asaad , et al. January 28, 2 | 2014-01-28 |
Generating Clock Signals For A Cycle Accurate, Cycle Reproducible Fpga Based Hardware Accelerator
App 20130262073 - Asaad; Sameth W. ; et al. | 2013-10-03 |
Cycle Accurate And Cycle Reproducible Memory For An Fpga Based Hardware Accelerator
App 20130262072 - Asaad; Sameth W. ; et al. | 2013-10-03 |
Wire Like Link For Cycle Reproducible And Cycle Accurate Hardware Accelerator
App 20130170525 - Asaad; Sameh ; et al. | 2013-07-04 |
Increasing Throughput Of Multiplexed Electrical Bus In Pipe-lined Architecture
App 20130070606 - Asaad; Sameh ; et al. | 2013-03-21 |
METHOD AND INFRASTRUCTURE FOR CYCLE-REPRODUCIBLE SIMULATION ON LARGE SCALE DIGITAL CIRCUITS ON A COORDINATED SET OF FIELD-PROGRAMMABLE GATE ARRAYS (FPGAs)
App 20120117413 - Asaad; Sameh W. ; et al. | 2012-05-10 |
Self-synchronizing pseudorandom bit sequence checker
Grant 7,757,142 - Kapur , et al. July 13, 2 | 2010-07-13 |
Clock scaling circuit
Grant 7,724,059 - Kapur May 25, 2 | 2010-05-25 |
Error type identification circuit for identifying different types of errors in communications devices
Grant 7,509,568 - Kapur , et al. March 24, 2 | 2009-03-24 |
Self-Synchronizing Pseudorandom Bit Sequence Checker
App 20080276139 - Kapur; Mohit ; et al. | 2008-11-06 |
Self-synchronizing pseudorandom bit sequence checker
Grant 7,412,640 - Kapur , et al. August 12, 2 | 2008-08-12 |
Testable digital delay line
App 20070038404 - Kapur; Mohit ; et al. | 2007-02-15 |
Testable digital delay line
Grant 7,177,775 - Kapur , et al. February 13, 2 | 2007-02-13 |
Testable digital delay line
App 20060247880 - Kapur; Mohit ; et al. | 2006-11-02 |
Error type identification circuit for identifying different types of errors in communications devices
App 20060156215 - Kapur; Mohit ; et al. | 2006-07-13 |
Clock scaling circuit
App 20060091928 - Kapur; Mohit | 2006-05-04 |
Self-synchronizing pseudorandom bit sequence checker
App 20050050419 - Kapur, Mohit ; et al. | 2005-03-03 |
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