Kapre; Ravindra M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kapre; Ravindra M..The latest application filed is for "silicon-oxide-nitride-oxide-silicon based multi-level non-volatile memory device and methods of operation thereof".

Company Profile

0.10.9

Kapre; Ravindra M. - San Jose CA
Kapre; Ravindra M - San Jose CA
Kapre; Ravindra M. - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Silicon-oxide-nitride-oxide-silicon Based Multi-level Non-volatile Memory Device And Methods Of Operation Thereof App 20220284951 - Prabhakar; Venkatraman ; et al.	2022-09-08
Silicon-oxide-nitride-oxide-silicon based multi-level non-volatile memory device and methods of operation thereof Grant 11,367,481 - Prabhakar , et al. June 21, 2	2022-06-21
Silicon-oxide-nitride-oxide-silicon Based Multi-level Non-volatile Memory Device And Methods Of Operation Thereof App 20210350850 - Prabhakar; Venkataraman ; et al.	2021-11-11
Combined Positive And Negative Voltage Electrostatic Discharge (esd) Protection Clamp With Cascoded Circuitry App 20210344193 - Rogers; David Michael ; et al.	2021-11-04
Memory cell array latchup prevention Grant 9,842,629 - Kapre , et al. December 12, 2	2017-12-12
Memory Cell Array Latchup Prevention App 20140211547 - Kapre; Ravindra M ; et al.	2014-07-31
Memory cell array latchup prevention Grant 8,493,804 - Kapre , et al. July 23, 2	2013-07-23
Memory Cell Array Latchup Prevention App 20130135954 - Kapre; Ravindra M. ; et al.	2013-05-30
Polycrystalline silicon activation RTA Grant 8,252,640 - Kapre , et al. August 28, 2	2012-08-28
Memory cell array Grant 8,045,410 - Kapre , et al. October 25, 2	2011-10-25
Memory cell array latchup prevention Grant 7,773,442 - Kapre , et al. August 10, 2	2010-08-10
Memory Cell Array App 20090213677 - Kapre; Ravindra M. ; et al.	2009-08-27
Memory cell array latchup prevention App 20050286295 - Kapre, Ravindra M. ; et al.	2005-12-29
Buried channel devices and a process for their fabrication simultaneously with surface channel devices to produce transistors and capacitors with multiple electrical gate oxides Grant 6,747,318 - Kapre , et al. June 8, 2	2004-06-08
Method Of Reducing Silicon Oxynitride Gate Insulator Thickness In Some Transistors Of A Hybrid Integrated Circuit To Obtain Increased Differential In Gate Insulator Thickness With Other Transistors Of The Hybrid Circuit Grant 6,656,805 - Kamath , et al. December 2, 2	2003-12-02
Method of reducing silicone oxynitride gate insulator thickness in some transistors of a hybrid integrated circuit to obtain increased differential in gate insulator thickness with other transistors of the hybrid circuit App 20030077866 - Kamath, Arvind ; et al.	2003-04-24
Method Of Reducing Silicon Oxynitride Gate Insulator Thickness In Some Transistors Of A Hybrid Integrated Circuit To Obtain Increased Differential In Gate Insulator Thickness With Other Transistors Of The Hybrid Circuit Grant 6,521,549 - Kamath , et al. February 18, 2	2003-02-18

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