Kapre; Ravindra

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kapre; Ravindra.The latest application filed is for "silicon-oxide-nitride-oxide-silicon multi-level non-volatile memory device and methods of fabrication thereof".

Company Profile

0.6.6

Kapre; Ravindra - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Silicon-oxide-nitride-oxide-silicon multi-level non-volatile memory device and methods of fabrication thereof Grant 11,355,185 - Ramkumar , et al. June 7, 2	2022-06-07
Silicon-oxide-nitride-oxide-silicon Based Multi-level Non-volatile Memory Device And Methods Of Operation Thereof App 20210158868 - Prabhakar; Venkataraman ; et al.	2021-05-27
Silicon-oxide-nitride-oxide-silicon Multi-level Non-volatile Memory Device And Methods Of Fabrication Thereof App 20210159346 - Ramkumar; Krishnaswamy ; et al.	2021-05-27
Silicon-oxide-nitride-oxide-silicon based multi level non-volatile memory device and methods of operation thereof Grant 11,017,851 - Prabhakar , et al. May 25, 2	2021-05-25
Memory Cell Array Latchup Prevention App 20140098598 - Kapre; RavIndra ; et al.	2014-04-10
Integration of non-volatile charge trap memory devices and logic CMOS devices Grant 8,143,129 - Ramkumar , et al. March 27, 2	2012-03-27
Integration of non-volatile charge trap memory devices and logic CMOS devices Grant 8,093,128 - Koutny, Jr. , et al. January 10, 2	2012-01-10
Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors Grant 7,629,653 - Sadoughi , et al. December 8, 2	2009-12-08
Integration Of Non-volatile Charge Trap Memory Devices And Logic Cmos Devices App 20080296661 - Ramkumar; Krishnaswamy ; et al.	2008-12-04
Integration Of Non-volatile Charge Trap Memory Devices And Logic Cmos Devices App 20080293207 - Koutny, JR.; William W.C. ; et al.	2008-11-27
Shared contact structures for integrated circuits App 20070210339 - Narasimhan; Geethakrishnan ; et al.	2007-09-13
Techniques for improving negative bias temperature instability (NBTI) lifetime of field effect transistors Grant 7,256,087 - Sadoughi , et al. August 14, 2	2007-08-14

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