Kapoor; Bhanu

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kapoor; Bhanu.The latest application filed is for "method, system, and computer program product for generating and verifying isolation logic modules in design of integrated circuits".

Company Profile

0.7.5

Kapoor; Bhanu - Richardson TX
Kapoor; Bhanu - San Jose CA
Kapoor; Bhanu - Irving TX
Kapoor; Bhanu - Dallas TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method, system, and computer program product for generating and verifying isolation logic modules in design of integrated circuits Grant 7,712,061 - Kapoor , et al. May 4, 2	2010-05-04
Method of optimization of clock gating in integrated circuit designs Grant 7,546,559 - Kapoor , et al. June 9, 2	2009-06-09
Method, System, And Computer Program Product For Generating And Verifying Isolation Logic Modules In Design Of Integrated Circuits App 20080098338 - Kapoor; Bhanu ; et al.	2008-04-24
Method, system and computer program product for generating and verifying isolation logic modules in design of integrated circuits Grant 7,349,835 - Kapoor , et al. March 25, 2	2008-03-25
Method, system, and computer program product for automatic insertion and correctness verification of level shifters in integrated circuits with multiple voltage domains Grant 7,152,216 - Kapoor , et al. December 19, 2	2006-12-19
A Method Of Optimization Of Clock Gating In Integrated Circuit Designs App 20060248487 - Kapoor; Bhanu ; et al.	2006-11-02
Identification and implementation of clock gating in the design of integrated circuits Grant 7,076,748 - Kapoor , et al. July 11, 2	2006-07-11
A Method, System, And Computer Program Product For Automatic Insertion And Correctness Verification Of Level Shifters In Integrated Circuits With Multiple Voltage Domains App 20060085770 - KAPOOR; Bhanu ; et al.	2006-04-20
A Method, System, And Computer Program Product For Generating And Verifying Isolation Logic Modules In Design Of Integrated Circuits App 20060064293 - KAPOOR; Bhanu ; et al.	2006-03-23
Identification and implementation of clock gating in the design of integrated circuits App 20050028118 - Kapoor, Bhanu ; et al.	2005-02-03
Low power video decoder system with block-based motion compensation Grant 5,978,509 - Nachtergaele , et al. November 2, 1	1999-11-02
Method of measuring activity in a digital circuit Grant 5,805,459 - Kapoor September 8, 1	1998-09-08

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.