| Patent | Date |
|---|
Reduced Variation MOSFET Using a Drain-Extension-Last Process
App 20160260816 - Kapoor; Ashok K. ; et al. | 2016-09-08 |
Reduced variation MOSFET using a drain-extension-last process
Grant 9,379,214 - Kapoor , et al. June 28, 2 | 2016-06-28 |
Reduced Variation MOSFET Using a Drain-Extension-Last Process
App 20150236117 - Kapoor; Ashok K. ; et al. | 2015-08-20 |
Variation resistant MOSFETs with superior epitaxial properties
Grant 9,012,276 - Kapoor , et al. April 21, 2 | 2015-04-21 |
Variation Resistant MOSFETs with Superior Epitaxial Properties
App 20150011056 - Kapoor; Ashok K. ; et al. | 2015-01-08 |
Random Doping Fluctuation Resistant FinFET
App 20140103437 - Kapoor; Ashok K. ; et al. | 2014-04-17 |
System and method for routing connections with improved interconnect thickness
Grant 8,042,076 - Zarkesh-Ha , et al. October 18, 2 | 2011-10-18 |
Junction field effect transistor (JFET) structure having top-to-bottom gate tie and method of manufacture
Grant 7,943,971 - Kapoor , et al. May 17, 2 | 2011-05-17 |
Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys
Grant 7,915,107 - Kapoor March 29, 2 | 2011-03-29 |
Semiconductor device having a fin structure and fabrication method thereof
Grant 7,772,619 - Kapoor August 10, 2 | 2010-08-10 |
Junction field effect transistor using a silicon on insulator architecture
Grant 7,772,620 - Kapoor August 10, 2 | 2010-08-10 |
Junction Field-Effect Transistor Having Insulator-Isolated Source/Drain Regions and Fabrication Method Therefor
App 20100171118 - Saha; Samar Kanti ; et al. | 2010-07-08 |
Method of forming an oxide isolated metal silicon-gate JFET
Grant 7,713,804 - Vora , et al. May 11, 2 | 2010-05-11 |
JFET device with improved off-state leakage current and method of fabrication
Grant 7,709,311 - Saha , et al. May 4, 2 | 2010-05-04 |
Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys
Grant 7,687,834 - Kapoor March 30, 2 | 2010-03-30 |
System and method for routing connections
Grant 7,689,964 - Zarkesh-Ha , et al. March 30, 2 | 2010-03-30 |
Junction Field Effect Transistor Using a Silicon on Insulator Architecture
App 20100019290 - Kapoor; Ashok K. | 2010-01-28 |
Junction Field Effect Transistor Using Silicide Connection Regions and Method of Fabrication
App 20100019289 - Kapoor; Ashok K. ; et al. | 2010-01-28 |
Integrated Circuit Using Complementary Junction Field Effect Transistor and MOS Transistor in Silicon and Silicon Alloys
App 20090311837 - Kapoor; Ashok K. | 2009-12-17 |
System And Method For Routing Connections With Improved Interconnect Thickness
App 20090282382 - Zarkesh-Ha; Payman ; et al. | 2009-11-12 |
Semiconductor device having strain-inducing substrate and fabrication methods thereof
Grant 7,605,031 - Kapoor October 20, 2 | 2009-10-20 |
Reduced Leakage Current Field-Effect Transistor Having Asymmetric Doping And Fabrication Method Therefor
App 20090206375 - Saha; Samar K. ; et al. | 2009-08-20 |
Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys
Grant 7,569,873 - Kapoor August 4, 2 | 2009-08-04 |
Static random access memory having cells with junction field effect and bipolar junction transistors
App 20090168508 - Kapoor; Ashok K. ; et al. | 2009-07-02 |
System And Method For Routing Connections
App 20090164963 - Zarkesh-Ha; Payman ; et al. | 2009-06-25 |
JFET Having a Step Channel Doping Profile and Method of Fabrication
App 20090137088 - Sonkusale; Sachin R. ; et al. | 2009-05-28 |
Semiconductor device having strain-inducing substrate and fabrication methods thereof
Grant 7,531,854 - Kapoor May 12, 2 | 2009-05-12 |
JFET device with virtual source and drain link regions and method of fabrication
Grant 7,525,136 - Saha , et al. April 28, 2 | 2009-04-28 |
JFET device with improved off-state leakage current and method of fabrication
Grant 7,525,138 - Saha , et al. April 28, 2 | 2009-04-28 |
Method for Applying a Stress Layer to a Semiconductor Device and Device Formed Therefrom
App 20090072278 - Kapoor; Ashok K. | 2009-03-19 |
Integrated Circuit Using Complementary Junction Field Effect Transistor and MOS Transistor in Silicon and Silicon Alloys
App 20090057727 - Kapoor; Ashok K. | 2009-03-05 |
Bipolar transistors having controllable temperature coefficient of current gain
Grant 7,482,642 - Kapoor January 27, 2 | 2009-01-27 |
Method for applying a stress layer to a semiconductor device and device formed therefrom
Grant 7,453,107 - Kapoor November 18, 2 | 2008-11-18 |
Method For Applying A Stress Layer To A Semiconductor Device And Device Formed Therefrom
App 20080272404 - Kapoor; Ashok K. | 2008-11-06 |
JFET Having a Step Channel Doping Profile and Method of Fabrication
App 20080272409 - Sonkusale; Sachin R. ; et al. | 2008-11-06 |
Inverted Junction Field Effect Transistor and Method of Forming Thereof
App 20080272401 - Vora; Madhu ; et al. | 2008-11-06 |
Small Geometry Mos Transistor With Thin Polycrystalline Surface Contacts And Method For Making
App 20080272439 - Kapoor; Ashok K. ; et al. | 2008-11-06 |
JFET Device With Improved Off-State Leakage Current and Method of Fabrication
App 20080272402 - Saha; Samar K. ; et al. | 2008-11-06 |
Semiconductor Device Having Strain-inducing Substrate And Fabrication Methods Thereof
App 20080272393 - Kapoor; Ashok K. | 2008-11-06 |
JFET Device With Virtual Source and Drain Link Regions and Method of Fabrication
App 20080272403 - Saha; Samar K. ; et al. | 2008-11-06 |
Semiconductor Device Having A Fin Structure And Fabrication Method Thereof
App 20080272407 - Kapoor; Ashok K. | 2008-11-06 |
Signaling circuit and method for integrated circuit devices and systems
App 20080237657 - Kapoor; Ashok K. | 2008-10-02 |
Scalable Process And Structure For JFET For Small And Decreasing Line Widths
App 20080093636 - Vora; Madhukar B. ; et al. | 2008-04-24 |
Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys
App 20070096144 - Kapoor; Ashok K. | 2007-05-03 |
Bipolar transistors having controllable temperature coefficient of current gain
App 20060202307 - Kapoor; Ashok K. | 2006-09-14 |
Programmable logic devices with silicon-germanium circuitry and associated methods
Grant 7,071,734 - Kapoor July 4, 2 | 2006-07-04 |
Automating photolithography in the fabrication of integrated circuits
Grant RE38,900 - Rostoker , et al. November 29, 2 | 2005-11-29 |
Provisioning and controlling medical instruments using wireless data communication
App 20050102167 - Kapoor, Ashok K. | 2005-05-12 |
Minimum metal consumption power distribution network on a bonded die
Grant 6,861,739 - Bhavnagarwala , et al. March 1, 2 | 2005-03-01 |
Routing technique to adjust clock skew using frames and prongs
Grant 6,741,122 - Kapoor , et al. May 25, 2 | 2004-05-25 |
Programmable logic devices with silicon-germanium circuitry and associated methods
App 20040070421 - Kapoor, Ashok K. | 2004-04-15 |
Routing technique to adjust clock skew
App 20030034832 - Kapoor, Ashok K. ; et al. | 2003-02-20 |
Hexagonal architecture
Grant 6,407,434 - Rostoker , et al. June 18, 2 | 2002-06-18 |
Insulated-gate field-effect transistors having different gate capacitances
Grant 6,300,663 - Kapoor October 9, 2 | 2001-10-09 |
Method for adjusting the density of lines and contact openings across a substrate region for improving the chemical-mechanical polishing of a thin-film later disposed thereon
Grant 6,109,775 - Tripathi , et al. August 29, 2 | 2000-08-29 |
Triangular semiconductor or gate
Grant 6,097,073 - Rostoker , et al. August 1, 2 | 2000-08-01 |
Process for forming self-aligned conductive plugs in multiple insulation levels in integrated circuit structures and resulting product
Grant 5,985,746 - Kapoor November 16, 1 | 1999-11-16 |
Architecture having diamond shaped or parallelogram shaped cells
Grant 5,973,376 - Rostoker , et al. October 26, 1 | 1999-10-26 |
Tri-directional interconnect architecture for SRAM
Grant 5,889,329 - Rostoker , et al. March 30, 1 | 1999-03-30 |
Method of forming a planar surface during multi-layer interconnect formation by a laser-assisted dielectric deposition
Grant 5,877,045 - Kapoor March 2, 1 | 1999-03-02 |
Hexagonal sense cell architecture
Grant 5,872,380 - Rostoker , et al. February 16, 1 | 1999-02-16 |
Triangular semiconductor NAND gate
Grant 5,864,165 - Rostoker , et al. January 26, 1 | 1999-01-26 |
Low dielectric constant insulation layer for integrated circuit structure and method of making same
Grant 5,864,172 - Kapoor , et al. January 26, 1 | 1999-01-26 |
Electrostatic discharge (ESD) structure and buffer driver structure for providing ESD and latchup protection for integrated circuit structures in minimized I/O space
Grant 5,835,986 - Wei , et al. November 10, 1 | 1998-11-10 |
Triangular semiconductor "AND" gate device
Grant 5,834,821 - Rostoker , et al. November 10, 1 | 1998-11-10 |
CAD for hexagonal architecture
Grant 5,822,214 - Rostoker , et al. October 13, 1 | 1998-10-13 |
Polydirectional non-orthoginal three layer interconnect architecture
Grant 5,808,330 - Rostoker , et al. September 15, 1 | 1998-09-15 |
Hexagonal SRAM architecture
Grant 5,801,422 - Rostoker , et al. September 1, 1 | 1998-09-01 |
Hexagonal architecture with triangular shaped cells
Grant 5,789,770 - Rostoker , et al. August 4, 1 | 1998-08-04 |
Method of forming polysilicon local interconnects
Grant 5,780,347 - Kapoor July 14, 1 | 1998-07-14 |
MOSFET device with improved LDD region and method of making same
Grant 5,780,350 - Kapoor July 14, 1 | 1998-07-14 |
Hexagonal field programmable gate array architecture
Grant 5,777,360 - Rostoker , et al. July 7, 1 | 1998-07-07 |
Self-aligned twin well process
Grant 5,770,492 - Kapoor June 23, 1 | 1998-06-23 |
Process for forming metal interconnect structures for use with integrated circuit devices to form integrated circuit structures
Grant 5,756,395 - Rostoker , et al. May 26, 1 | 1998-05-26 |
Hexagonal DRAM array
Grant 5,742,086 - Rostoker , et al. April 21, 1 | 1998-04-21 |
Automating photolithography in the fabrication of integrated circuits
Grant 5,663,076 - Rostoker , et al. September 2, 1 | 1997-09-02 |
Integrated circuit structure having floating electrode with discontinuous phase of metal silicide formed on a surface thereof and process for making same
Grant 5,650,648 - Kapoor July 22, 1 | 1997-07-22 |
Microelectronic integrated circuit including triangular CMOS "nand" gate device
Grant 5,650,653 - Rostoker , et al. July 22, 1 | 1997-07-22 |
Metal interconnect structures for use with integrated circuit devices to form integrated circuit structures
Grant 5,640,049 - Rostoker , et al. June 17, 1 | 1997-06-17 |
Method of making combined JFET & MOS transistor device
Grant 5,631,176 - Kapoor May 20, 1 | 1997-05-20 |
Low dielectric constant insulation layer for integrated circuit structure and method of making same
Grant 5,598,026 - Kapoor , et al. January 28, 1 | 1997-01-28 |
Self-aligned twin well process having a SiO.sub.2 -polysilicon-SiO.sub.2 barrier mask
Grant 5,583,062 - Kapoor December 10, 1 | 1996-12-10 |
Active device constructed in opening formed in insulation layer
Grant 5,523,600 - Kapoor June 4, 1 | 1996-06-04 |
Process for active device constructed in opening formed in insulation layer with a resistor
Grant 5,521,117 - Kapoor May 28, 1 | 1996-05-28 |
Integrated circuit structure having floating electrode with discontinuous phase of metal silicide formed on a surface thereof and process for making same
Grant 5,498,558 - Kapoor March 12, 1 | 1996-03-12 |
Low dielectric constant insulation layer for integrated circuit structure and method of making same
Grant 5,494,859 - Kapoor February 27, 1 | 1996-02-27 |
Process for formation of vias (or contact openings) and fuses in the same insulation layer with minimal additional steps
Grant 5,472,901 - Kapoor December 5, 1 | 1995-12-05 |
Low dielectric constant insulation layer for integrated circuit structure and method of making same
Grant 5,470,801 - Kapoor , et al. November 28, 1 | 1995-11-28 |
Process for forming low dielectric constant insulation layer on integrated circuit structure
Grant 5,393,712 - Rostoker , et al. February 28, 1 | 1995-02-28 |
Active device constructed in opening formed in insulation layer and process for making same
Grant 5,391,505 - Kapoor February 21, 1 | 1995-02-21 |
Method of making extended silicide and external contact
Grant 5,229,307 - Vora , et al. July 20, 1 | 1993-07-20 |
Sidewall contact bipolar transistor with controlled lateral spread of selectively grown epitaxial layer
Grant 5,166,767 - Kapoor , et al. November 24, 1 | 1992-11-24 |
Method of fabricating a base-coupled transistor logic
Grant 5,166,094 - Kapoor November 24, 1 | 1992-11-24 |
Process for forming self-aligned silicide base contact for bipolar transistor
Grant 5,098,854 - Kapoor , et al. March 24, 1 | 1992-03-24 |
Extended silicide and external contact technology
Grant 5,045,916 - Vor , et al. September 3, 1 | 1991-09-03 |
Structure for inhibiting dopant out-diffusion
Grant 4,829,363 - Thomas , et al. May 9, 1 | 1989-05-09 |
Method of fabricating polycrystalline silicon resistors having desired temperature coefficients
Grant 4,762,801 - Kapoor August 9, 1 | 1988-08-09 |
Method and structure for inhibiting dopant out-diffusion
Grant 4,640,004 - Thomas , et al. February 3, 1 | 1987-02-03 |
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