| Patent | Date |
|---|
Multiprocessor computer systems with command FIFO buffer at each target device
Grant 6,647,450 - Kaplinsky November 11, 2 | 2003-11-11 |
Configurable I/O circuitry defining virtual ports
Grant 6,212,591 - Kaplinsky April 3, 2 | 2001-04-03 |
Low power, static content addressable memory
Grant 6,188,629 - Kaplinsky February 13, 2 | 2001-02-13 |
Inverter-controlled digital interface circuit with dual switching points for increased speed
Grant 5,920,210 - Kaplinsky July 6, 1 | 1999-07-06 |
Programmable logic device with partial switch matrix and bypass mechanism
Grant 5,796,268 - Kaplinsky August 18, 1 | 1998-08-18 |
Programmable dynamic line-termination circuit
Grant 5,726,583 - Kaplinsky March 10, 1 | 1998-03-10 |
Low noise tri-state output buffer
Grant 5,568,062 - Kaplinsky October 22, 1 | 1996-10-22 |
Memory system for loading peripherals on power up
Grant 5,455,923 - Kaplinsky October 3, 1 | 1995-10-03 |
Write circuit for CMOS latch and memory systems
Grant 5,298,816 - Kaplinsky March 29, 1 | 1994-03-29 |
Clock distribution circuit with active de-skewing
Grant 5,298,866 - Kaplinsky March 29, 1 | 1994-03-29 |
Programmable logic device
Grant RE34,444 - Kaplinsky November 16, 1 | 1993-11-16 |
Low power multifunction logic array
Grant 5,250,859 - Kaplinsky October 5, 1 | 1993-10-05 |
Programmable CMOS flip-flop emptying multiplexers
Grant 5,164,612 - Kaplinsky November 17, 1 | 1992-11-17 |
System having a host independent input/output processor for controlling data transfer between a memory and a plurality of I/O controllers
Grant 5,131,081 - MacKenna , et al. July 14, 1 | 1992-07-14 |
Programmable logic device with programmable inverters at input/output pads
Grant 5,028,821 - Kaplinsky July 2, 1 | 1991-07-02 |
Programmable logic device with ganged output pins
Grant 5,023,606 - Kaplinsky * June 11, 1 | 1991-06-11 |
Logic gates with a programmable number of inputs
Grant 5,012,135 - Kaplinsky April 30, 1 | 1991-04-30 |
Programmable logic expander
Grant 4,967,107 - Kaplinsky October 30, 1 | 1990-10-30 |
Configuration control circuit for programmable logic devices
Grant 4,940,909 - Mulder , et al. July 10, 1 | 1990-07-10 |
Data processing apparatus for time-interleaved execution of a plurality of processes
Grant 4,853,845 - Zimmer , et al. August 1, 1 | 1989-08-01 |
Programmable logic device
Grant 4,847,612 - Kaplinsky July 11, 1 | 1989-07-11 |
Raster scan video controller with programmable prioritized sharing of display memory between update and display processes and programmable memory access termination
Grant 4,782,462 - Kaplinsky , et al. November 1, 1 | 1988-11-01 |
Guarded regions for controlling memory access
Grant 4,677,546 - Freeman , et al. June 30, 1 | 1987-06-30 |
Memory access controller
Grant 4,669,043 - Kaplinsky May 26, 1 | 1987-05-26 |
Communication system having an information bus and circuits therefor
Grant 4,429,384 - Kaplinsky January 31, 1 | 1984-01-31 |
Device for increasing the length of a logic computer address
Grant 4,361,868 - Kaplinsky November 30, 1 | 1982-11-30 |
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