Kanzelman; Robert Lowell

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kanzelman; Robert Lowell.The latest application filed is for "computer program product for extending incremental verification of circuit design to encompass verification restraints".

Company Profile

0.24.25

Kanzelman; Robert Lowell - Rochester MN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Computer program product for design verification using sequential and combinational transformations Grant 7,996,800 - Baumgarter , et al. August 9, 2	2011-08-09
Incremental design reduction via iterative overapproximation and re-encoding strategies Grant 7,930,672 - Baumgartner , et al. April 19, 2	2011-04-19
Enhanced verification through binary decision diagram-based target decomposition Grant 7,921,394 - Baumgartner , et al. April 5, 2	2011-04-05
Reduction of XOR/XNOR subexpressions in structural design representations Grant 7,913,218 - Baumgartner , et al. March 22, 2	2011-03-22
Enhanced verification through binary decision diagram-based target decomposition using state analysis extraction Grant 7,908,575 - Baumgartner , et al. March 15, 2	2011-03-15
Method and system for reduction of AND/OR subexpressions in structural design representations Grant 7,882,459 - Baumgartner , et al. February 1, 2	2011-02-01
Method and system for reduction of XOR/XNOR subexpressions in structural design representations Grant 7,831,937 - Baumgartner , et al. November 9, 2	2010-11-09
Method and system for reduction of and/or subexpressions in structural design representations Grant 7,823,093 - Baumgartner , et al. October 26, 2	2010-10-26
Computer program product for extending incremental verification of circuit design to encompass verification restraints Grant 7,779,378 - Baumgartner , et al. August 17, 2	2010-08-17
Extending incremental verification of circuit design to encompass verification restraints Grant 7,509,605 - Baumgartner , et al. March 24, 2	2009-03-24
Computer Program Product for Extending Incremental Verification of Circuit Design to Encompass Verification Restraints App 20090049416 - Baumgartner; Jason Raymond ; et al.	2009-02-19
Computer program product for design verification using sequential and combinational transformations App 20080178132 - Baumgarter; Jason Raymond ; et al.	2008-07-24
System and Program Product for Incremental Design Reduction via Iterative Overapproximation and Re-Encoding Strategies App 20080127002 - Baumgartner; Jason Raymond ; et al.	2008-05-29
Method and system for reduction of and/or subexpressions in structural design representations Grant 7,380,221 - Baumgartner , et al. May 27, 2	2008-05-27
Method for incremental design reduction via iterative overapproximation and re-encoding strategies Grant 7,370,292 - Baumgartner , et al. May 6, 2	2008-05-06
Method and System for Enhanced Verification Through Structural Target Decomposition App 20080104558 - Baumgartner; Jason Raymond ; et al.	2008-05-01
Method and System for Enhanced Verification Through Structural Target Decomposition App 20080104559 - Baumgartner; Jason R. ; et al.	2008-05-01
Method and System for Reduction of XOR/XNOR Subexpressions in Structural Design Representations App 20080091386 - Baumgartner; Jason Raymond ; et al.	2008-04-17
Method and system for reduction of XOR/XNOR subexpressions in structural design representations App 20080092091 - Baumgartner; Jason Raymond ; et al.	2008-04-17
Design verification using sequential and combinational transformations Grant 7,360,185 - Baumgarter , et al. April 15, 2	2008-04-15
Method and system for enchanced verification through binary decision diagram-based target decomposition App 20080086707 - Baumgartner; Jason Raymond ; et al.	2008-04-10
Method and system for enhanced verification through structural target decomposition Grant 7,350,169 - Baumgartner , et al. March 25, 2	2008-03-25
Method and System for Reduction of AND/OR Subexpressions in Structural Design Representations App 20080072186 - Baumgartner; Jason Raymond ; et al.	2008-03-20
Method and System for Reduction of AND/OR Subexpressions in Structural Design Representations App 20080072185 - Baumgartner; Jason Raymond ; et al.	2008-03-20
Method and system for enhanced verification through binary decision diagram-based target decomposition Grant 7,343,573 - Baumgartner , et al. March 11, 2	2008-03-11
Method and system for reduction of XOR/XNOR subexpressions in structural design representations Grant 7,340,694 - Baumgartner , et al. March 4, 2	2008-03-04
Method And System For Enchanced Verification Through Binary Decision Diagram-based Target Decomposition App 20080052648 - Baumgartner; Jason Raymond ; et al.	2008-02-28
System and method for engine-controlled case splitting within multiple-engine based verification framework Grant 7,266,795 - Baumgartner , et al. September 4, 2	2007-09-04
Exploiting suspected redundancy for enhanced design verification Grant 7,260,799 - Baumgartner , et al. August 21, 2	2007-08-21
Extending incremental verification of circuit design to encompass verification restraints App 20070136701 - Baumgartner; Jason Raymond ; et al.	2007-06-14
Equivalence checking of scan path flush operations Grant 7,210,109 - Caron , et al. April 24, 2	2007-04-24
Method and system for enhanced verification through binary decision diagram-based target decomposition App 20060277508 - Baumgartner; Jason Raymond ; et al.	2006-12-07
Method and system for enhanced verification through structural target decomposition App 20060277507 - Baumgartner; Jason Raymond ; et al.	2006-12-07
System and method for engine-controlled case splitting within a multiple-engine based verification framework App 20060230370 - Baumgartner; Jason Raymond ; et al.	2006-10-12
Method and system for reduction of XOR/XNOR subexpressions in structural design representations App 20060230366 - Baumgartner; Jason Raymond ; et al.	2006-10-12
Method and system for reduction of and/or subexpressions in structural design representations App 20060230367 - Baumgartner; Jason Raymond ; et al.	2006-10-12
Design verification using sequential and combinational transformations App 20060190869 - Baumgartner; Jason Raymond ; et al.	2006-08-24
Exploiting suspected redundancy for enhanced design verification App 20060190873 - Baumgartner; Jason Raymond ; et al.	2006-08-24
Incremental, assertion-based design verification Grant 7,093,218 - Baumgartner , et al. August 15, 2	2006-08-15
Method for incremental design reduction via iterative overapproximation and re-encoding strategies App 20060129952 - Baumgartner; Jason Raymond ; et al.	2006-06-15
Equivalence checking of scan path flush operations App 20050289486 - Caron, Kenneth Michael ; et al.	2005-12-29
Incremental, assertion-based design verification App 20050188337 - Baumgartner, Jason Raymond ; et al.	2005-08-25
Apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs Grant 6,763,505 - Baumgartner , et al. July 13, 2	2004-07-13
Apparatus and method for removing effects of phase abstraction from a phase abstracted trace Grant 6,748,573 - Baumgartner , et al. June 8, 2	2004-06-08
Apparatus and method for representing gated-clock latches for phase abstraction Grant 6,745,377 - Baumgartner , et al. June 1, 2	2004-06-01
Apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs App 20030192018 - Baumgartner, Jason Raymond ; et al.	2003-10-09
Apparatus and method for removing effects of phase abstraction from a phase abstracted trace App 20030192016 - Baumgartner, Jason Raymond ; et al.	2003-10-09
Apparatus and method for representing gated-clock latches for phase abstraction App 20030192017 - Baumgartner, Jason Raymond ; et al.	2003-10-09
Simplified buffer manipulation using standard repowering function Grant 5,799,170 - Drumm , et al. August 25, 1	1998-08-25

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