Kant; Shree

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kant; Shree.The latest application filed is for "efficient implementation of a read scheme for multi-threaded register file".

Company Profile

0.12.7

Kant; Shree - Union City CA US
Kant; Shree - Fremont CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Adaptive timing control circuitry to address leakage Grant 8,482,316 - Liu , et al. July 9, 2	2013-07-09
Method for performing swap operation and apparatus for implementing the same Grant 7,484,061 - Liu , et al. January 27, 2	2009-01-27
Method and pipeline architecture for processing multiple swap requests to reduce latency Grant 7,337,305 - Tam , et al. February 26, 2	2008-02-26
Efficient implementation of a read scheme for multi-threaded register file Grant 7,203,100 - Kant , et al. April 10, 2	2007-04-10
Efficient method of data transfer between register files and memories Grant 7,136,308 - Kant , et al. November 14, 2	2006-11-14
Efficient method of data transfer between register files and memories App 20060092710 - Kant; Shree ; et al.	2006-05-04
Efficient implementation of a read scheme for multi-threaded register file App 20060092711 - Kant; Shree ; et al.	2006-05-04
Methods and circuits for balancing bitline precharge Grant 6,940,771 - Kant , et al. September 6, 2	2005-09-06
High speed single ended sense amplifier with built-in multiplexer Grant 6,900,668 - Tam , et al. May 31, 2	2005-05-31
Internal pipeline architecture for save/restore operation to reduce latency App 20050114634 - Tam, Kenway W. ; et al.	2005-05-26
High Speed Single Ended Sense Amplifier With Built-in Multiplexer App 20050110527 - Tam, Kenway W. ; et al.	2005-05-26
Methods and circuits for balancing bitline precharge App 20040151044 - Kant, Shree ; et al.	2004-08-05
Low power memory design with asymmetric bit line driver Grant 6,707,721 - Singh , et al. March 16, 2	2004-03-16
High performance address decode technique for arrays Grant 6,646,951 - Kant , et al. November 11, 2	2003-11-11
Low power memory design with asymmetric bit line driver App 20030174535 - Singh, Gajendra ; et al.	2003-09-18
High performance address decode technique for arrays App 20030076732 - Kant, Shree ; et al.	2003-04-24
Decoding of a register file Grant 6,320,813 - Kant November 20, 2	2001-11-20
Method for sizing PMOS pull-up devices Grant 6,316,301 - Kant November 13, 2	2001-11-13

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