loadpatents
name:-0.019690036773682
name:-0.022891998291016
name:-0.016083002090454
Kanike; Narasimhulu Patent Filings

Kanike; Narasimhulu

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kanike; Narasimhulu.The latest application filed is for "back silicided variable capacitor devices".

Company Profile
14.26.22
  • Kanike; Narasimhulu - San Diego CA
  • Kanike; Narasimhulu - irvine CA
  • Kanike; Narasimhulu - Wayne NJ US
  • Kanike; Narasimhulu - Wappingers Falls NY
  • Kanike; Narasimhulu - Lake Hiawatha NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Buried oxide transcap devices
Grant 10,840,387 - Marino , et al. November 17, 2
2020-11-17
Variable capacitor flat-band voltage engineering
Grant 10,622,492 - Marino , et al.
2020-04-14
Back silicided variable capacitor devices
Grant 10,608,124 - Goktepeli , et al.
2020-03-31
Back Silicided Variable Capacitor Devices
App 20190326448 - GOKTEPELI; Sinan ;   et al.
2019-10-24
Buried Oxide Transcap Devices
App 20190312152 - MARINO; Fabio Alessio ;   et al.
2019-10-10
Apparatuses And Methods For A Variable Capacitor
App 20190305143 - MARINO; Fabio Alessio ;   et al.
2019-10-03
Lateral devices in silicon-on-insulator (SOI) technology
Grant 10,424,641 - Liang , et al. Sept
2019-09-24
Non-volatile memory structure in silicon-on-insulator (SOI) technology
Grant 10,418,465 - Liang , et al. Sept
2019-09-17
Metal-oxide Semiconductor (mos) Device With Thick Oxide
App 20190280125 - KANIKE; Narasimhulu ;   et al.
2019-09-12
Variable Capacitor Flat-band Voltage Engineering
App 20190221677 - MARINO; Fabio Alessio ;   et al.
2019-07-18
Metal-oxide semiconductor (MOS) device with thick oxide
Grant 10,355,134 - Kanike , et al. July 16, 2
2019-07-16
Layout techniques for transcap area optimization
Grant 10,319,866 - Marino , et al.
2019-06-11
Transcap device architecture with reduced control voltage and improved quality factor
Grant 10,211,347 - Marino , et al. Feb
2019-02-19
Transcap manufacturing techniques without a silicide-blocking mask
Grant 10,181,533 - Marino , et al. Ja
2019-01-15
Variable Capacitor Linearity Improvement Through Doping Engineering
App 20190006530 - MARINO; Fabio Alessio ;   et al.
2019-01-03
Transcap Device Architecture With Reduced Control Voltage And Improved Quality Factor
App 20180374963 - MARINO; Fabio Alessio ;   et al.
2018-12-27
Metal-oxide Semiconductor (mos) Device With Thick Oxide
App 20180342620 - KANIKE; Narasimhulu ;   et al.
2018-11-29
Advanced Techniques To Manipulate The C-v Characteristics Of Variable Capacitors
App 20180240915 - MARINO; Fabio Alessio ;   et al.
2018-08-23
Transcap Manufacturing Techniques Without A Silicide-blocking Mask
App 20180233605 - MARINO; Fabio Alessio ;   et al.
2018-08-16
Layout Techniques For Transcap Area Optimization
App 20180233603 - MARINO; Fabio Alessio ;   et al.
2018-08-16
Variable capacitor structures with reduced channel resistance
Grant 9,985,145 - Liang , et al. May 29, 2
2018-05-29
Transcap manufacturing techniques without a silicide-blocking mask
Grant 9,882,066 - Marino , et al. January 30, 2
2018-01-30
INTEGRATED CIRCUIT (IC) CHIP HAVING BOTH METAL AND SILICON GATE FIELD EFFECT TRANSISTORs (FETs) AND METHOD OF MANUFACTURE
App 20150325647 - Kanike; Narasimhulu
2015-11-12
Integrated circuit (IC) chip having both metal and silicon gate field effect transistors (FETs) and method of manufacture
Grant 9,012,283 - Kanike April 21, 2
2015-04-21
Method of manufacturing a body-contacted SOI FINFET
Grant 8,993,402 - Kanike , et al. March 31, 2
2015-03-31
High threshold voltage NMOS transistors for low power IC technology
Grant 8,969,969 - Chan , et al. March 3, 2
2015-03-03
High threshold voltage NMOS transistors for low power IC technology
Grant 8,927,361 - Booth, Jr. , et al. January 6, 2
2015-01-06
Integration of fin-based devices and ETSOI devices
Grant 8,779,511 - Kanike , et al. July 15, 2
2014-07-15
Method of Manufacturing a Body-Contacted SOI FINFET
App 20140048881 - Kanike; Narasimhulu ;   et al.
2014-02-20
High Threshold Voltage Nmos Transistors For Low Power Ic Technology
App 20130196476 - Booth, JR.; Roger Allen ;   et al.
2013-08-01
Poly resistor and metal gate fabrication and structure
Grant 8,377,763 - Kanike February 19, 2
2013-02-19
Method of fabricating an embedded polysilicon resistor and an embedded eFuse isolated from a substrate
Grant 8,377,790 - Kanike , et al. February 19, 2
2013-02-19
Integrated Circuit (IC) Chip Having Both Metal and Silicon Gate Field Effect Transistors (FETs) and Method of Manufacture
App 20120292664 - Kanike; Narasimhulu
2012-11-22
Integration Of Fin-based Devices And Etsoi Devices
App 20120261756 - Kanike; Narasimhulu ;   et al.
2012-10-18
Integration of fin-based devices and ETSOI devices
Grant 8,236,634 - Kanike , et al. August 7, 2
2012-08-07
METHOD OF FABRICATION BODIES FOR AN EMBEDDED POLYSILICON RESISTOR AND AN EMBEDDED eFUSE ISOLATED FROM A SUBSTRATE
App 20120196423 - Kanike; Narasimhulu ;   et al.
2012-08-02
Poly Resistor and Metal Gate Fabrication and Structure
App 20120139049 - Kanike; Narasimhulu
2012-06-07
Semiconductor embedded resistor generation
Grant 8,012,821 - Ryou , et al. September 6, 2
2011-09-06
High Threshold Voltage NMOS Transistors For Low Power IC Technology
App 20100237425 - Chan; Victor W.C. ;   et al.
2010-09-23
Semiconductor Embedded Resistor Generation
App 20100197106 - Ryou; Choongryul ;   et al.
2010-08-05

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