loadpatents
name:-0.0097799301147461
name:-0.0097541809082031
name:-0.00062012672424316
Kane; Terence Patent Filings

Kane; Terence

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kane; Terence.The latest application filed is for "specific site backside underlaying and micromasking method for electrical characterization of semiconductor devices".

Company Profile
0.8.8
  • Kane; Terence - Wappingers Falls NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Bilayer HDP CVD/PE CVD cap in advanced BEOL interconnect structures and method thereof
Grant 6,914,320 - Chen , et al. July 5, 2
2005-07-05
Specific site backside underlaying and micromasking method for electrical characterization of semiconductor devices
Grant 6,894,522 - Averill , et al. May 17, 2
2005-05-17
Bilayer HDP CVD/PE CVD cap in advance BEOL interconnect structures and method thereof
Grant 6,887,783 - Chen , et al. May 3, 2
2005-05-03
Site-specific methodology for localization and analyzing junction defects in mosfet devices
Grant 6,884,641 - Bruley , et al. April 26, 2
2005-04-26
Specific Site Backside Underlaying And Micromasking Method For Electrical Characterization Of Semiconductor Devices
App 20050073333 - Averill, Barbara A. ;   et al.
2005-04-07
Site-specific Methodology For Localization And Analyzing Junction Defects In Mosfet Devices
App 20050064610 - BRULEY, JOHN ;   et al.
2005-03-24
Method for electrically characterizing charge sensitive semiconductor devices
Grant 6,858,530 - Kane , et al. February 22, 2
2005-02-22
Backside integrated circuit die surface finishing technique and tool
Grant 6,852,629 - Kane , et al. February 8, 2
2005-02-08
Backside integrated circuit die surface finishing technique and tool
Grant 6,790,125 - Kane , et al. September 14, 2
2004-09-14
Bilayer HDP CVD / PE CVD cap in advanced BEOL interconnect structures and method thereof
App 20040173907 - Chen, Tze-Chiang ;   et al.
2004-09-09
Backside integrated circuit die surface finishing technique and tool
App 20040137738 - Kane, Terence ;   et al.
2004-07-15
Structure and method for charge sensitive electrical devices
App 20040089952 - Kane, Terence ;   et al.
2004-05-13
Structure and method for charge sensitive electrical devices
Grant 6,670,717 - Kane , et al. December 30, 2
2003-12-30
Bilayer HDP CVD / PE CVD cap in advanced BEOL interconnect structures and method thereof
App 20030134499 - Chen, Tze-Chiang ;   et al.
2003-07-17
Structure and method for charge sensitive electrical devices
App 20030071361 - Kane, Terence ;   et al.
2003-04-17
Backside integrated circuit die surface finishing technique and tool
App 20020072308 - Kane, Terence ;   et al.
2002-06-13

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