loadpatents
Patent applications and USPTO patent grants for Kandala; Aravind.The latest application filed is for "performing multiple bit computation and convolution in memory".
Patent | Date |
---|---|
Performing Multiple Bit Computation and Convolution in Memory App 20220156045 - Nazar; Shahzad ;   et al. | 2022-05-19 |
Low power double pumped multi-port register file architecture Grant 9,361,959 - Bhatia , et al. June 7, 2 | 2016-06-07 |
Low Power Double Pumped Multi-port Register File Architecture App 20160055889 - Bhatia; Ajay Kumar ;   et al. | 2016-02-25 |
Apparatus to suppress concurrent read and write word line access of the same memory element in a memory array Grant 9,001,593 - Gupta , et al. April 7, 2 | 2015-04-07 |
Apparatus To Suppress Concurrent Read And Write Word Line Access Of The Same Memory Element In A Memory Array App 20140177346 - Gupta; Hitesh ;   et al. | 2014-06-26 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.