loadpatents
name:-0.025693893432617
name:-0.022792816162109
name:-0.002086877822876
Kanakasabapathy; Sivananda Patent Filings

Kanakasabapathy; Sivananda

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kanakasabapathy; Sivananda.The latest application filed is for "low undercut n-p work function metal patterning in nanosheet replacement metal gate process".

Company Profile
1.32.31
  • Kanakasabapathy; Sivananda - Pleasanton CA
  • Kanakasabapathy; Sivananda - Niskayuna NY
  • Kanakasabapathy; Sivananda - Schenectady NY
  • Kanakasabapathy; Sivananda - Albany NY
  • Kanakasabapathy; Sivananda - Armonk NY US
  • Kanakasabapathy; Sivananda - Hopewell Junction NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Low undercut N-P work function metal patterning in nanosheet replacement metal gate process
Grant 10,629,495 - Seshadri , et al.
2020-04-21
Low Undercut N-p Work Function Metal Patterning In Nanosheet Replacement Metal Gate Process
App 20190214311 - Seshadri; Indira ;   et al.
2019-07-11
Low undercut N-P work function metal patterning in nanosheet replacement metal gate process
Grant 10,276,452 - Seshadri , et al.
2019-04-30
Double diffusion break gate structure without vestigial antenna capacitance
Grant 10,115,724 - Reznicek , et al. October 30, 2
2018-10-30
Double diffusion break gate structure without vestigial antenna capacitance
Grant 10,083,964 - Reznicek , et al. September 25, 2
2018-09-25
Method for controlled recessing of materials in cavities in IC devices
Grant 9,589,850 - Park , et al. March 7, 2
2017-03-07
Method for forming merged contact for semiconductor device
Grant 9,431,399 - Alptekin , et al. August 30, 2
2016-08-30
Structure and method to realize conformal doping in deep trench applications
Grant 9,064,744 - Basker , et al. June 23, 2
2015-06-23
Method of eDRAM DT strap formation in FinFET device structure
Grant 8,946,802 - Basker , et al. February 3, 2
2015-02-03
Method of eDRAM DT strap formation in FinFET device structure
Grant 8,927,365 - Basker , et al. January 6, 2
2015-01-06
High performance non-planar semiconductor devices with metal filled inter-fin gaps
Grant 8,901,667 - Jagannathan , et al. December 2, 2
2014-12-02
Structure and method to integrate embedded DRAM with FinFET
Grant 8,753,934 - Kanakasabapathy , et al. June 17, 2
2014-06-17
Sidewall image transfer process with multiple critical dimensions
Grant 8,673,165 - Raghunathan , et al. March 18, 2
2014-03-18
High Performance Non-planar Semiconductor Devices With Metal Filled Inter-fin Gaps
App 20140061815 - JAGANNATHAN; HEMANTH ;   et al.
2014-03-06
High performance non-planar semiconductor devices with metal filled inter-fin gaps
Grant 8,653,610 - Jagannathan , et al. February 18, 2
2014-02-18
Structure And Method To Realize Conformal Doping In Deep Trench Applications
App 20140038382 - Basker; Veeraraghavan S. ;   et al.
2014-02-06
Structure And Method To Realize Conformal Doping In Deep Trench Applications
App 20140035038 - Basker; Veeraraghavan S. ;   et al.
2014-02-06
Method of eDRAM DT Strap Formation In FinFET Device Structure
App 20140030864 - BASKER; Veeraraghavan S. ;   et al.
2014-01-30
Method of eDRAM DT Strap Formation in FinFET Device Structure
App 20140027831 - Basker; Veeraraghavan S. ;   et al.
2014-01-30
Method For Fabricating Transistor With Recessed Channel And Raised Source/drain
App 20140017859 - CHENG; Kangguo ;   et al.
2014-01-16
Method of making a semiconductor device
Grant 8,586,478 - Soda , et al. November 19, 2
2013-11-19
Single metal gate CMOS integration by intermixing polarity specific capping layers
Grant 8,541,275 - Kanakasabapathy , et al. September 24, 2
2013-09-24
Transistor With Recessed Channel And Raised Source/drain
App 20130175579 - Cheng; Kangguo ;   et al.
2013-07-11
Method For Fabricating Transistor With Recessed Channel And Raised Source/drain
App 20130178022 - CHENG; Kangguo ;   et al.
2013-07-11
Structure and method to integrate embedded DRAM with finfet
Grant 8,421,139 - Kanakasabapathy , et al. April 16, 2
2013-04-16
Sidewall Image Transfer Process With Multiple Critical Dimensions
App 20130089984 - Raghunathan; Sudharshanan ;   et al.
2013-04-11
Structure And Method To Integrate Embedded Dram With Finfet
App 20130005129 - KANAKASABAPATHY; Sivananda ;   et al.
2013-01-03
Method Of Making A Semiconductor Device
App 20120329268 - SODA; Eiichi ;   et al.
2012-12-27
Structure And Method For Low Temperature Gate Stack For Advanced Substrates
App 20120139014 - Bedell; Stephen W. ;   et al.
2012-06-07
Method for semiconductor gate hardmask removal and decoupling of implants
Grant 8,133,746 - Kanakasabapathy , et al. March 13, 2
2012-03-13
Stacked magnetic devices
Grant 8,120,946 - Kanakasabapathy , et al. February 21, 2
2012-02-21
High Performance Non-Planar Semiconductor Devices with Metal Filled Inter-Fin Gaps
App 20110260257 - Jagannathan; Hemanth ;   et al.
2011-10-27
Structure And Method To Integrate Embedded Dram With Finfet
App 20110248326 - KANAKASABAPATHY; SIVANANDA ;   et al.
2011-10-13
Method For Semiconductor Gate Hardmask Removal And Decoupling Of Implants
App 20110212548 - KANAKASABAPATHY; SIVANANDA ;   et al.
2011-09-01
Single Metal Gate Cmos Integration By Intermixing Polarity Specific Capping Layers
App 20110108921 - KANAKASABAPATHY; SIVANANDA ;   et al.
2011-05-12
Resist stripping methods using backfilling material layer
Grant 7,935,637 - Fuller , et al. May 3, 2
2011-05-03
Dielectric spacer removal
Grant 7,919,379 - Cartier , et al. April 5, 2
2011-04-05
Method and apparatus for bitline and contact via integration in magnetic random access memory arrays
Grant 7,772,663 - Kanakasabapathy , et al. August 10, 2
2010-08-10
Stacked Magnetic Devices
App 20090279354 - Kanakasabapathy; Sivananda ;   et al.
2009-11-12
Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit
Grant 7,531,367 - Assefa , et al. May 12, 2
2009-05-12
Dielectric Spacer Removal
App 20090065817 - Cartier; Eduard A. ;   et al.
2009-03-12
Resist Stripping Methods Using Backfilling Material Layer
App 20090047784 - Fuller; Nicholas C.M. ;   et al.
2009-02-19
Structure and method for formation of cladded interconnects for MRAMs
Grant 7,442,647 - Kanakasabapathy , et al. October 28, 2
2008-10-28
Utilizing Sidewall Spacer Features to Form Magnetic Tunnel Junctions in an Integrated Circuit
App 20080211055 - Assefa; Solomon ;   et al.
2008-09-04
Method And Apparatus For Bitline And Contact Via Integration In Magnetic Random Access Memory Arrays
App 20080198647 - Kanakasabapathy; Sivananda ;   et al.
2008-08-21
Utilizing sidewall spacer features to form magnetic tunnel junctions in an integrated circuit
App 20070166840 - Assefa; Solomon ;   et al.
2007-07-19
Stacked magnetic devices
App 20060092688 - Kanakasabapathy; Sivananda ;   et al.
2006-05-04

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