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Patent applications and USPTO patent grants for Kan; Chia-Chia.The latest application filed is for "wafer-level testing method and test structure thereof".
Patent | Date |
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Wafer-level testing method and test structure thereof Grant 11,121,046 - Lee , et al. September 14, 2 | 2021-09-14 |
Wafer-level Testing Method And Test Structure Thereof App 20200043815 - LEE; PEI-HSUAN ;   et al. | 2020-02-06 |
Ultra-high voltage laterally-diffused MOS devices and methods of forming the same Grant 9,184,282 - Huang , et al. November 10, 2 | 2015-11-10 |
Ultra-High Voltage Laterally-Diffused MOS Devices and Methods of Forming the Same App 20150041891 - Huang; Tzu-Ming ;   et al. | 2015-02-12 |
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