| Patent | Date |
|---|
Three-dimensional (3D) integrated circuit device having a backside power delivery network
Grant 11,444,068 - Song , et al. September 13, 2 | 2022-09-13 |
Three-dimensional (3d) Integrated Circuit Device Having A Backside Power Delivery Network
App 20220020735 - SONG; Stanley Seungchul ; et al. | 2022-01-20 |
Power Distribution Networks For A Three-dimensional (3d) Integrated Circuit (ic) (3dic)
App 20190027435 - Kamal; Pratyush ; et al. | 2019-01-24 |
Power distribution networks for a three-dimensional (3D) integrated circuit (IC) (3DIC)
Grant 10,121,743 - Kamal , et al. November 6, 2 | 2018-11-06 |
Power Distribution Networks For A Three-dimensional (3d) Integrated Circuit (ic) (3dic)
App 20180286800 - Kamal; Pratyush ; et al. | 2018-10-04 |
Silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) standard library cell circuits having a gate back-bias rail(s), and related systems and methods
Grant 10,062,680 - Kamal , et al. August 28, 2 | 2018-08-28 |
Connection propagation for inter-logical block connections in integrated circuits
Grant 9,929,733 - Kamal , et al. March 27, 2 | 2018-03-27 |
Power gate placement techniques in three-dimensional (3D) integrated circuits (ICs) (3DICs)
Grant 9,754,923 - Xie , et al. September 5, 2 | 2017-09-05 |
Three dimensional logic circuit
Grant 9,537,471 - Kamal January 3, 2 | 2017-01-03 |
Clock tree synthesis for low cost pre-bond testing of 3D integrated circuits
Grant 9,508,615 - Lim , et al. November 29, 2 | 2016-11-29 |
Clock Tree Synthesis For Low Cost Pre-bond Testing Of 3d Integrated Circuits
App 20160233134 - LIM; Sung Kyu ; et al. | 2016-08-11 |
Three Dimensional Logic Circuit
App 20160233853 - KAMAL; Pratyush | 2016-08-11 |
High Quality Physical Design For Monolithic Three-dimensional Integrated Circuits (3d Ic) Using Two-dimensional Integrated Circuit (2d Ic) Design Tools
App 20160042110 - LIM; Sung Kyu ; et al. | 2016-02-11 |
Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems, methods and related components
Grant 9,213,358 - Kamal , et al. December 15, 2 | 2015-12-15 |
PLACEMENT OF MONOLITHIC INTER-TIER VIAS (MIVs) WITHIN MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) USING CLUSTERING TO INCREASE USABLE WHITESPAC
App 20150333005 - Samadi; Kambiz ; et al. | 2015-11-19 |
Silicon-on-insulator (soi) Complementary Metal Oxide Semiconductor (cmos) Standard Library Cell Circuits Having A Gate Back-bias Rail(s), And Related Systems And Methods
App 20150325563 - Kamal; Pratyush ; et al. | 2015-11-12 |
Monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) with vertical memory components, related systems and methods
Grant 9,147,438 - Kamal , et al. September 29, 2 | 2015-09-29 |
Placement of monolithic inter-tier vias (MIVs) within monolithic three dimensional (3D) integrated circuits (ICs) (3DICs) using clustering to increase usable whitespace
Grant 9,123,721 - Samadi , et al. September 1, 2 | 2015-09-01 |
Length-of-diffusion protected circuit and method of design
Grant 9,093,995 - Bellur , et al. July 28, 2 | 2015-07-28 |
Decoupling capacitor for integrated circuit
Grant 9,053,960 - Kamal , et al. June 9, 2 | 2015-06-09 |
PLACEMENT OF MONOLITHIC INTER-TIER VIAS (MIVs) WITHIN MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) USING CLUSTERING TO INCREASE USABLE WHITESPACE
App 20150145143 - Samadi; Kambiz ; et al. | 2015-05-28 |
Monolithic Three Dimensional (3d) Integrated Circuit (ic) (3dic) Cross-tier Clock Skew Management Systems, Methods And Related Components
App 20150121327 - Kamal; Pratyush ; et al. | 2015-04-30 |
METHODS OF DESIGNING THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) AND RELATED SYSTEMS AND COMPONENTS
App 20150112646 - Kamal; Pratyush ; et al. | 2015-04-23 |
MONOLITHIC THREE DIMENSIONAL (3D) INTEGRATED CIRCUITS (ICs) (3DICs) WITH VERTICAL MEMORY COMPONENTS, RELATED SYSTEMS AND METHODS
App 20150109843 - Kamal; Pratyush ; et al. | 2015-04-23 |
Monolithic three dimensional (3D) flip-flops with minimal clock skew and related systems and methods
Grant 9,013,235 - Kamal , et al. April 21, 2 | 2015-04-21 |
Monolithic Three Dimensional (3d) Flip-flops With Minimal Clock Skew And Related Systems And Methods
App 20150022250 - Kamal; Pratyush ; et al. | 2015-01-22 |
Monolithic Three Dimensional (3d) Random Access Memory (ram) Array Architecture With Bitcell And Logic Partitioning
App 20150019802 - Kamal; Pratyush ; et al. | 2015-01-15 |
Length-of-diffusion Protected Circuit And Method Of Design
App 20140354338 - Bellur; Kashyap Ramachandra ; et al. | 2014-12-04 |
Shared-diffusion standard cell architecture
Grant 8,836,040 - Kamal , et al. September 16, 2 | 2014-09-16 |
Decoupling Capacitor For Integrated Circuit
App 20140246715 - Kamal; Pratyush ; et al. | 2014-09-04 |
Shared-diffusion Standard Cell Architecture
App 20140124868 - Kamal; Pratyush ; et al. | 2014-05-08 |
Standard cell architecture using double poly patterning for multi VT devices
Grant 8,610,176 - Patel , et al. December 17, 2 | 2013-12-17 |
Method and apparatus for characterizing and reducing proximity effect on cell electrical characteristics
Grant 8,584,075 - Datta , et al. November 12, 2 | 2013-11-12 |
Area Efficient Gridded Polysilicon Layouts
App 20130032885 - Swamynathan; Chethan ; et al. | 2013-02-07 |
Method and Apparatus for Characterizing and Reducing Proximity Effect on Cell Electrical Characteristics
App 20120210284 - Datta; Animesh ; et al. | 2012-08-16 |
Standard Cell Architecture Using Double Poly Patterning for Multi VT Devices
App 20120180016 - Chidambaram; PR ; et al. | 2012-07-12 |
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