Kalafatis; Stavros

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kalafatis; Stavros.The latest application filed is for "method and system to insert a flow marker into an instruction stream to indicate a thread switching operation within a multithreaded processor".

Company Profile

0.13.8

Kalafatis; Stavros - Portland OR
Kalafatis; Stavros - Hillsboro OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Qualification of event detection by thread ID and thread privilege level Grant 7,448,025 - Kalafatis , et al. November 4, 2	2008-11-04
Method and apparatus for thread switching within a multithreaded processor Grant 6,981,261 - Kalafatis , et al. December 27, 2	2005-12-27
Method and system to perform a thread switching operation within a multithreaded processor based on dispatch of a quantity of instruction information for a full instruction Grant 6,971,104 - Kalafatis , et al. November 29, 2	2005-11-29
Method and system to insert a flow marker into an instruction stream to indicate a thread switching operation within a multithreaded processor Grant 6,865,740 - Kalafatis , et al. March 8, 2	2005-03-08
Method and system to perform a thread switching operation within a multithreaded processor based on detection of a flow marker within an instruction information Grant 6,854,118 - Kalafatis , et al. February 8, 2	2005-02-08
Method and system to perform a thread switching operation within a multithreaded processor based on detection of a stall condition Grant 6,850,961 - Kalafatis , et al. February 1, 2	2005-02-01
Method and system to perform a thread switching operation within a multithreaded processor based on detection of a branch instruction Grant 6,795,845 - Kalafatis , et al. September 21, 2	2004-09-21
Method and system to perform a thread switching operation within a multithreaded processor based on detection of the absence of a flow of instruction information for a thread Grant 6,785,890 - Kalafatis , et al. August 31, 2	2004-08-31
Method and apparatus for thread switching within a multithreaded processor Grant 6,535,905 - Kalafatis , et al. March 18, 2	2003-03-18
Method and system to perform a thread switching operation within a multithreaded processor based on dispatch of a quantity of instruction information for a full instruction App 20030023835 - Kalafatis, Stavros ; et al.	2003-01-30
Method and system to perform a thread switching operation within a multithreaded processor based on detection of the absence of a flow of instruction information for a thread App 20030023658 - Kalafatis, Stavros ; et al.	2003-01-30
Method and apparatus for thread switching within a multithreaded processor App 20030023659 - Kalafatis, Stavros ; et al.	2003-01-30
Method and system to insert a flow marker into an instruction stream to indicate a thread switching operation within a multithreaded processor App 20030023834 - Kalafatis, Stavros ; et al.	2003-01-30
Method and system to perform a thread switching operation within a multithreaded processor based on detection of a branch instruction App 20030018685 - Kalafatis, Stavros ; et al.	2003-01-23
Method and system to perform a thread switching operation within a multithreaded processor based on detection of a stall condition App 20030018686 - Kalafatis, Stavros ; et al.	2003-01-23
Method and system to perform a thread switching operation within a multithreaded processor based on detection of a flow marker within an instruction information App 20030018687 - Kalafatis, Stavros ; et al.	2003-01-23
Qualification of event detection by thread ID and thread privilege level App 20020124237 - Sprunt, Brinkley ; et al.	2002-09-05
System and method of maintaining and utilizing multiple return stack buffers Grant 6,374,350 - D'Sa , et al. April 16, 2	2002-04-16
System and method of maintaining and utilizing multiple return stack buffers Grant 6,151,671 - D'Sa , et al. November 21, 2	2000-11-21
System and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline units Grant 6,055,630 - D'Sa , et al. April 25, 2	2000-04-25
Dual edge adjusting digital phase-locked loop having one-half reference clock jitter Grant 5,546,434 - Kalafatis August 13, 1	1996-08-13

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