KAJIWARA; Jun

Patent Applications and Registrations

Patent applications and USPTO patent grants for KAJIWARA; Jun.The latest application filed is for "absorbent article".

Company Profile

0.13.15

KAJIWARA; Jun - Utsunomiya-shi Tochigi
Kajiwara; Jun - Yawata JP
Kajiwara; Jun - Kyoto JP
Kajiwara, Jun - Yawata-shi JP
Kajiwara, Jun - Kyoto-Shi JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Absorbent Article App 20210100695 - ISHIBASHI; Kyoko ; et al.	2021-04-08
Pixel arranging apparatus, solid-state image sensing apparatus, and camera Grant 7,750,957 - Shimazu , et al. July 6, 2	2010-07-06
Method for detecting vertical transfer defects in image sensors Grant 7,551,213 - Nakashima , et al. June 23, 2	2009-06-23
Panel interface device, LSI for image processing, digital camera and digital equipment App 20080055201 - Kajiwara; Jun	2008-03-06
Image processing method App 20050253939 - Nakashima, Toshiyuki ; et al.	2005-11-17
Focus adjusting device and focus adjusting method App 20050253954 - Nakashima, Toshiyuki ; et al.	2005-11-17
Image processing device and image processing method App 20050253936 - Kogishi, Toshiya ; et al.	2005-11-17
Multi-chip module, semiconductor chip, and interchip connection test method for multi-chip module Grant 6,914,259 - Sakiyama , et al. July 5, 2	2005-07-05
Pixel arranging apparatus, solid-state image sensing apparatus,and camera App 20050104982 - Shimazu, Yoshihisa ; et al.	2005-05-19
Multichip module structure Grant 6,833,626 - Kajiwara , et al. December 21, 2	2004-12-21
Potential generating circuit, potential generating device and semiconductor device using the same, and driving method thereof Grant 6,809,953 - Toyoda , et al. October 26, 2	2004-10-26
Power supply voltage detection circuit Grant 6,686,782 - Kinoshita , et al. February 3, 2	2004-02-03
Method for designing power supply circuit and semiconductor chip Grant 6,684,378 - Yamamoto , et al. January 27, 2	2004-01-27
Semiconductor chip and multi-chip module Grant 6,646,342 - Sakiyama , et al. November 11, 2	2003-11-11
Potential generating circuit, potential generating device and semiconductor device using the same, and driving method thereof App 20030197548 - Toyoda, Kenji ; et al.	2003-10-23
Power source system for reducing power consumption in an intermittent mode of operation Grant 6,531,856 - Sakiyama , et al. March 11, 2	2003-03-11
Power supply device App 20030011247 - Kajiwara, Jun ; et al.	2003-01-16
Multichip module and method for testing connection of the module App 20030008424 - Kajiwara, Jun ; et al.	2003-01-09
Cell library database and design aiding system Grant 6,490,715 - Moriwaki , et al. December 3, 2	2002-12-03
Semiconductor chip and multi-chip module App 20020149034 - Sakiyama, Shiro ; et al.	2002-10-17
Switching regulator and LSI system Grant 6,429,633 - Kajiwara , et al. August 6, 2	2002-08-06
Power supply voltage detection circuit App 20020101263 - Kinoshita, Masayoshi ; et al.	2002-08-01
Semiconductor chip, set of semiconductor chips and multichip module App 20020079591 - Sakiyama, Shiro ; et al.	2002-06-27
Switching Regulator And Lsi System App 20020053897 - KAJIWARA, JUN ; et al.	2002-05-09
Method for designing power supply circuit and semiconductor chip App 20020042902 - Yamamoto, Akira ; et al.	2002-04-11
Power source system App 20020030474 - Sakiyama, Shiro ; et al.	2002-03-14
Switching regulator DC/DC converter, and LSI system provided with switching regulator Grant 6,307,360 - Kajiwara , et al. October 23, 2	2001-10-23
Power circuit including inrush current limiter, and integrated circuit including the power circuit Grant 6,150,800 - Kinoshita , et al. November 21, 2	2000-11-21

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.