loadpatents
name:-0.17837500572205
name:-0.11081600189209
name:-0.03384804725647
Kai; James Patent Filings

Kai; James

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kai; James.The latest application filed is for "non-volatile memory with memory array between circuits".

Company Profile
45.115.102
  • Kai; James - Santa Clara CA
  • Kai; James - Fremont CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Three-dimensional memory device employing thinned insulating layers and methods for forming the same
Grant 11,398,496 - Kai , et al. July 26, 2
2022-07-26
Non-volatile Memory With Memory Array Between Circuits
App 20220229588 - Dutta; Deepanshu ;   et al.
2022-07-21
Three dimensional ferroelectric memory
Grant 11,380,709 - Dong , et al. July 5, 2
2022-07-05
Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer
Grant 11,355,486 - Mizutani , et al. June 7, 2
2022-06-07
Bonded Semiconductor Die Assembly Containing Through-stack Via Structures And Methods For Making The Same
App 20220028846 - ALSMEIER; Johann ;   et al.
2022-01-27
Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer
Grant 11,201,107 - Okina , et al. December 14, 2
2021-12-14
Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer
Grant 11,195,857 - Kai , et al. December 7, 2
2021-12-07
Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer
Grant 11,195,781 - Okina , et al. December 7, 2
2021-12-07
Three-dimensional Memory Device With Wiggled Drain-select-level Isolation Structure And Methods Of Manufacturing The Same
App 20210358946 - PULUGURTHA; Srinivas ;   et al.
2021-11-18
Three-dimensional Memory Device Employing Thinned Insulating Layers And Methods For Forming The Same
App 20210335999 - KAI; James ;   et al.
2021-10-28
Three-dimensional Memory Device Employing Thinned Insulating Layers And Methods For Forming The Same
App 20210335805 - KAI; James ;   et al.
2021-10-28
Method for removing a bulk substrate from a bonded assembly of wafers
Grant 11,127,729 - Kai , et al. September 21, 2
2021-09-21
Three-dimensional Memory Device With Dielectric Isolated Via Structures And Methods Of Making The Same
App 20210210503 - MATSUNO; Koichi ;   et al.
2021-07-08
Three-dimensional memory device including self-aligned dielectric isolation regions for connection via structures and method of making the same
Grant 11,043,455 - Kai , et al. June 22, 2
2021-06-22
Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same
Grant 11,037,943 - Imai , et al. June 15, 2
2021-06-15
Three-dimensional memory device containing alternating stack of source layers and drain layers and vertical gate electrodes
Grant 11,018,153 - Kai , et al. May 25, 2
2021-05-25
Three-dimensional device with bonded structures including a support die and methods of making the same
Grant 10,985,169 - Kai , et al. April 20, 2
2021-04-20
Three-dimensional memory device containing alternating stack of source layers and drain layers and vertical gate electrodes
Grant 10,950,626 - Kai , et al. March 16, 2
2021-03-16
Three-dimensional memory device with drain-select-level isolation structures and method of making the same
Grant 10,943,917 - Iwai , et al. March 9, 2
2021-03-09
Three-dimensional Memory Device Containing Alternating Stack Of Source Layers And Drain Layers And Vertical Gate Electrodes
App 20210050359 - KAI; James ;   et al.
2021-02-18
Three-dimensional Memory Device Containing Alternating Stack Of Source Layers And Drain Layers And Vertical Gate Electrodes
App 20210050360 - KAI; James ;   et al.
2021-02-18
Bonded Three-dimensional Memory Devices And Methods Of Making The Same By Replacing Carrier Substrate With Source Layer
App 20210035965 - MIZUTANI; Yuki ;   et al.
2021-02-04
Three-dimensional Memory Device Including Self-aligned Dielectric Isolation Regions For Connection Via Structures And Method Of Making The Same
App 20210028111 - KAI; James ;   et al.
2021-01-28
Three-dimensional Memory Device Having On-pitch Drain Select Gate Electrodes And Method Of Making The Same
App 20210005617 - KAI; James ;   et al.
2021-01-07
Through-array conductive via structures for a three-dimensional memory device and methods of making the same
Grant 10,840,260 - Kai , et al. November 17, 2
2020-11-17
Method For Removing A Bulk Substrate From A Bonded Assembly Of Wafers
App 20200357783 - Kai; James ;   et al.
2020-11-12
Non-volatile memory with pool capacitor
Grant 10,825,827 - Dunga , et al. November 3, 2
2020-11-03
Non-volatile memory with pool capacitor
Grant 10,818,685 - Dunga , et al. October 27, 2
2020-10-27
Three-dimensional Device With Bonded Structures Including A Support Die And Methods Of Making The Same
App 20200286905 - KAI; James ;   et al.
2020-09-10
Three-dimensional memory device containing bond pad-based power supply network for a source line and methods of making the same
Grant 10,748,894 - Chowdhury , et al. A
2020-08-18
Three-dimensional memory device with drain-select-level isolation structures and method of making the same
Grant 10,748,927 - Tsutsumi , et al. A
2020-08-18
Bonded Three-dimensional Memory Devices And Methods Of Making The Same By Replacing Carrier Substrate With Source Layer
App 20200258816 - A1
2020-08-13
Bonded Three-dimensional Memory Devices And Methods Of Making The Same By Replacing Carrier Substrate With Source Layer
App 20200258904 - A1
2020-08-13
Bonded Three-dimensional Memory Devices And Methods Of Making The Same By Replacing Carrier Substrate With Source Layer
App 20200258817 - A1
2020-08-13
Three-dimensional Memory Device With Drain-select-level Isolation Structures And Method Of Making The Same
App 20200251489 - Kind Code
2020-08-06
Three-dimensional Memory Device With Drain-select-level Isolation Structures And Method Of Making The Same
App 20200251488 - Kind Code
2020-08-06
Method for removing a bulk substrate from a bonded assembly of wafers
Grant 10,727,216 - Kai , et al.
2020-07-28
Three-dimensional Memory Device Containing Bond Pad-based Power Supply Network For A Source Line And Methods Of Making The Same
App 20200235090 - CHOWDHURY; Murshed ;   et al.
2020-07-23
Through-array Conductive Via Structures For A Three-dimensional Memory Device And Methods Of Making The Same
App 20200235120 - KAI; James ;   et al.
2020-07-23
Three-dimensional memory device with drain-select-level isolation structures and method of making the same
Grant 10,685,979 - Lu , et al.
2020-06-16
Three-dimensional memory device with drain-select-level isolation structures and method of making the same
Grant 10,685,978 - Lu , et al.
2020-06-16
Bonded three-dimensional memory devices and methods of making the same by replacing carrier substrate with source layer
Grant 10,629,616 - Kai , et al.
2020-04-21
Three-dimensional memory device including contact via structures that extend through word lines and method of making the same
Grant 10,622,369 - Zhou , et al.
2020-04-14
Three-dimensional memory device with semicircular metal-semiconductor alloy floating gate electrodes and methods of making thereof
Grant 10,622,368 - Kanakamedala , et al.
2020-04-14
Three Dimensional Ferroelectric Memory
App 20200075631 - Dong; Yingda ;   et al.
2020-03-05
Three-dimensional flat inverse NAND memory device and method of making the same
Grant 10,559,588 - Dong , et al. Feb
2020-02-11
Non-volatile Memory With Pool Capacitor
App 20200013795 - Dunga; Mohan ;   et al.
2020-01-09
Non-volatile Memory With Pool Capacitor
App 20200013794 - Dunga; Mohan ;   et al.
2020-01-09
Three-dimensional Memory Device With Semicircular Metal-semiconductor Alloy Floating Gate Electrodes And Methods Of Making There
App 20190371803 - Kanakamedala; Senaka ;   et al.
2019-12-05
Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof
Grant 10,490,568 - Kai , et al. Nov
2019-11-26
Three-dimensional memory device and method of making the same using concurrent formation of memory openings and contact openings
Grant 10,490,569 - Mushiga , et al. Nov
2019-11-26
Grouping memory cells into sub-blocks for program speed uniformity
Grant 10,431,313 - Zhang , et al. O
2019-10-01
Concurrent Formation Of Memory Openings And Contact Openings For A Three-dimensional Memory Device
App 20190280002 - Kai; James ;   et al.
2019-09-12
Three-dimensional Memory Device And Method Of Making The Same Using Concurrent Formation Of Memory Openings And Contact Openings
App 20190280003 - Mushiga; Mitsuteru ;   et al.
2019-09-12
Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same
Grant 10,403,639 - Orimoto , et al. Sep
2019-09-03
Three-dimensional Memory Device Having On-pitch Drain Select Gate Electrodes And Method Of Making The Same
App 20190267391 - IMAI; Muneyuki ;   et al.
2019-08-29
Concurrent formation of memory openings and contact openings for a three-dimensional memory device
Grant 10,388,666 - Kai , et al. A
2019-08-20
Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device
Grant 10,381,443 - Matsumoto , et al. A
2019-08-13
Three-dimensional Memory Device Including Contact Via Structures That Extend Through Word Lines And Method Of Making The Same
App 20190229125 - Zhou; Fei ;   et al.
2019-07-25
Three-dimensional Flat Inverse Nand Memory Device And Method Of Making The Same
App 20190221575 - Dong; Yingda ;   et al.
2019-07-18
Concurrent formation of memory openings and contact openings for a three-dimensional memory device
Grant 10,355,009 - Kai , et al. July 16, 2
2019-07-16
Three-dimensional NAND memory device with common bit line for multiple NAND strings in each memory block
Grant 10,355,015 - Zhang , et al. July 16, 2
2019-07-16
Three-dimensional memory device having on-pitch drain select gate electrodes and method of making the same
Grant 10,297,610 - Kai , et al.
2019-05-21
Three-dimensional memory device containing floating gate select transistor
Grant 10,290,643 - Kai , et al.
2019-05-14
Mid-plane word line switch connection for CMOS under three-dimensional memory device and method of making thereof
Grant 10,269,817 - Ogawa , et al.
2019-04-23
Three-dimensional array device having a metal containing barrier and method of making thereof
Grant 10,262,945 - Makala , et al.
2019-04-16
High voltage field effect transistor with laterally extended gate dielectric and method of making thereof
Grant 10,224,407 - Chowdhury , et al.
2019-03-05
Three-dimensional Memory Device Having On-pitch Drain Select Gate Electrodes And Method Of Making The Same
App 20190027489 - ORIMOTO; Takashi ;   et al.
2019-01-24
Three-dimensional Memory Device Having On-pitch Drain Select Gate Electrodes And Method Of Making The Same
App 20190027488 - KAI; James ;   et al.
2019-01-24
Mid-plane Word Line Switch Connection For Cmos Under Three-dimensional Memory Device And Method Of Making Thereof
App 20180350825 - Ogawa; Hiroyuki ;   et al.
2018-12-06
Three-dimensional memory device having epitaxial germanium-containing vertical channel and method of making thereof
Grant 10,121,794 - Gunji-Yoneoka , et al. November 6, 2
2018-11-06
Bulb-shaped Memory Stack Structures For Direct Source Contact In Three-dimensional Memory Device
App 20180261671 - Matsumoto; Kazuyo ;   et al.
2018-09-13
High Voltage Field Effect Transistor With Laterally Extended Gate Dielectric And Method Of Making Thereof
App 20180248013 - CHOWDHURY; Murshed ;   et al.
2018-08-30
Grouping Memory Cells Into Sub-blocks For Program Speed Uniformity
App 20180240527 - Zhang; Zhengyi ;   et al.
2018-08-23
Three-dimensional Nand Memory Device With Common Bit Line For Multiple Nand Strings In Each Memory Block
App 20180233513 - Zhang; Yanli ;   et al.
2018-08-16
Three-dimensional memory device having drain select level isolation structure and method of making thereof
Grant 10,050,054 - Zhang , et al. August 14, 2
2018-08-14
Through-memory-level via structures for a three-dimensional memory device
Grant 10,038,006 - Furihata , et al. July 31, 2
2018-07-31
Three-dimensional Memory Device With Self-aligned Drain Side Select Gate Electrodes And Method Of Making Thereof
App 20180211970 - Kai; James ;   et al.
2018-07-26
Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device
Grant 10,020,363 - Ogawa , et al. July 10, 2
2018-07-10
Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device
Grant 10,008,570 - Yu , et al. June 26, 2
2018-06-26
Three-dimensional Array Device Having A Metal Containing Barrier And Method Of Making Thereof
App 20180151497 - MAKALA; Raghuveer S. ;   et al.
2018-05-31
Bulb-shaped memory stack structures for direct source contact in three-dimensional memory device
Grant 9,985,098 - Matsumoto , et al. May 29, 2
2018-05-29
Three-dimensional Memory Device With Self-aligned Drain Side Select Gate Electrodes And Method Of Making Thereof
App 20180138189 - KAI; James ;   et al.
2018-05-17
Three-dimensional memory device with self-aligned drain side select gate electrodes and method of making thereof
Grant 9,972,640 - Kai , et al. May 15, 2
2018-05-15
Bulb-shaped Memory Stack Structures For Direct Source Contact In Three-dimensional Memory Device
App 20180122905 - Ogawa; Hiroyuki ;   et al.
2018-05-03
Bulb-shaped Memory Stack Structures For Direct Source Contact In Three-dimensional Memory Device
App 20180122906 - YU; Jixin ;   et al.
2018-05-03
Bulb-shaped Memory Stack Structures For Direct Source Contact In Three-dimensional Memory Device
App 20180122904 - Matsumoto; Kazuyo ;   et al.
2018-05-03
Grouping memory cells into sub-blocks for program speed uniformity
Grant 9,959,932 - Zhang , et al. May 1, 2
2018-05-01
Mid-plane word line switch connection for CMOS under three-dimensional memory device and method of making thereof
Grant 9,953,992 - Ogawa , et al. April 24, 2
2018-04-24
Three-dimensional Memory Device Having Drain Select Level Isolation Structure And Method Of Making Thereof
App 20180097009 - ZHANG; Yanli ;   et al.
2018-04-05
Within array replacement openings for a three-dimensional memory device
Grant 9,935,123 - Nishikawa , et al. April 3, 2
2018-04-03
Three-dimensional memory device containing separately formed drain select transistors and method of making thereof
Grant 9,922,987 - Mizutani , et al. March 20, 2
2018-03-20
Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same
Grant 9,917,100 - Zhang , et al. March 13, 2
2018-03-13
Three-dimensional Memory Device Having Epitaxial Germanium-containing Vertical Channel And Method Of Making Thereof
App 20170365613 - GUNJI-YONEOKA; Marika ;   et al.
2017-12-21
Three-dimensional NAND device containing support pedestal structures for a buried source line and method of making the same
Grant 9,831,266 - Kai , et al. November 28, 2
2017-11-28
Three-dimensional memory device containing a lateral source contact and method of making the same
Grant 9,824,966 - Kanakamedala , et al. November 21, 2
2017-11-21
Through-memory-level via structures for a three-dimensional memory device
Grant 9,818,693 - Toyama , et al. November 14, 2
2017-11-14
Through-memory-level via structures for a three-dimensional memory device
Grant 9,818,759 - Kai , et al. November 14, 2
2017-11-14
Three-dimensional memory device with charge carrier injection wells for vertical channels and method of making and using thereof
Grant 9,805,805 - Zhang , et al. October 31, 2
2017-10-31
Non-volatile memory with flat cell structures and air gap isolation
Grant 9,698,149 - Purayath , et al. July 4, 2
2017-07-04
Through-memory-level Via Structures For A Three-dimensional Memory Device
App 20170179154 - FURIHATA; Yoko ;   et al.
2017-06-22
Through-memory-level Via Structures For A Three-dimensional Memory Device
App 20170179151 - Kai; James ;   et al.
2017-06-22
Through-memory-level Via Structures For A Three-dimensional Memory Device
App 20170179026 - Toyama; Fumiaki ;   et al.
2017-06-22
Within Array Replacement Openings For A Three-dimensional Memory Device
App 20170148808 - NISHIKAWA; Masatoshi ;   et al.
2017-05-25
Three-dimensional Nand Device Containing Support Pedestal Structures For A Buried Source Line And Method Of Making The Same
App 20170148811 - ZHANG; Tong ;   et al.
2017-05-25
Three-dimensional Nand Device Containing Support Pedestal Structures For A Buried Source Line And Method Of Making The Same
App 20170148810 - Kai; James ;   et al.
2017-05-25
Monolithic three-dimensional NAND strings and methods of fabrication thereof
Grant 9,576,975 - Zhang , et al. February 21, 2
2017-02-21
Trench vertical NAND and method of making thereof
Grant 9,552,991 - Matsudaira , et al. January 24, 2
2017-01-24
Non-volatile storage element with suspended charge storage region
Grant 9,548,311 - Lee , et al. January 17, 2
2017-01-17
Three dimensional vertical NAND device with floating gates
Grant 9,524,779 - Kai , et al. December 20, 2
2016-12-20
Multi tier three-dimensional memory devices including vertically shared bit lines
Grant 9,502,471 - Lu , et al. November 22, 2
2016-11-22
Method of making a vertical NAND device using a sacrificial layer with air gap and sequential etching of multilayer stacks
Grant 9,449,982 - Lu , et al. September 20, 2
2016-09-20
Non-Volatile Storage Element With Suspended Charge Storage Region
App 20160240546 - Lee; Donovan ;   et al.
2016-08-18
Non-volatile storage element with suspended charge storage region
Grant 9,349,740 - Lee , et al. May 24, 2
2016-05-24
Monolithic Three-dimensional Nand Strings And Methods Of Fabrication Thereof
App 20160086972 - ZHANG; Yanli ;   et al.
2016-03-24
NAND string containing self-aligned control gate sidewall cladding
Grant 9,230,971 - Lee , et al. January 5, 2
2016-01-05
Inverted-T word line and formation for non-volatile storage
Grant 9,224,746 - Purayath , et al. December 29, 2
2015-12-29
Three Dimensional Vertical NAND Device With Floating Gates
App 20150371709 - Kai; James ;   et al.
2015-12-24
Trench Vertical Nand And Method Of Making Thereof
App 20150318298 - Matsudaira; Akira ;   et al.
2015-11-05
Vertical Floating Gate Nand With Offset Dual Control Gates
App 20150318295 - Kai; James ;   et al.
2015-11-05
Memory device with control gate oxygen diffusion control and method of making thereof
Grant 9,177,808 - Purayath , et al. November 3, 2
2015-11-03
Three dimensional NAND device with silicide containing floating gates and method of making thereof
Grant 9,165,940 - Chien , et al. October 20, 2
2015-10-20
Method Of Making A Vertical Nand Device Using A Sacrificial Layer With Air Gap And Sequential Etching Of Multilayer Stacks
App 20150294978 - LU; Zhenyu ;   et al.
2015-10-15
Method of forming an active area with floating gate negative offset profile in FG NAND memory
Grant 9,099,496 - Tian , et al. August 4, 2
2015-08-04
Non-volatile Storage Element With Suspended Charge Storage Region
App 20150214235 - Lee; Donovan ;   et al.
2015-07-30
Nand String Containing Self-aligned Control Gate Sidewall Cladding
App 20150137208 - Lee; Donovan ;   et al.
2015-05-21
Non-volatile memory structure containing nanodots and continuous metal layer charge traps and method of making thereof
Grant 9,029,936 - Purayath , et al. May 12, 2
2015-05-12
Non-Volatile Memory With Flat Cell Structures And Air Gap Isolation
App 20150123191 - Purayath; Vinod Robert ;   et al.
2015-05-07
Method for using nanoparticles to make uniform discrete floating gate layer
Grant 8,987,802 - Lee , et al. March 24, 2
2015-03-24
Three Dimensional Nand Device With Silicide Containing Floating Gates And Method Of Making Thereof
App 20150072488 - Chien; Henry ;   et al.
2015-03-12
NAND string containing self-aligned control gate sidewall cladding
Grant 8,969,153 - Lee , et al. March 3, 2
2015-03-03
Method of forming a floating gate with a wide base and a narrow stem
Grant 8,946,803 - Matamis , et al. February 3, 2
2015-02-03
Method of fabricating non-volatile memory with flat cell structures and air gap isolation
Grant 8,946,048 - Purayath , et al. February 3, 2
2015-02-03
Three dimensional NAND device with silicide containing floating gates
Grant 8,928,061 - Chien , et al. January 6, 2
2015-01-06
Nand String Containing Self-aligned Control Gate Sidewall Cladding
App 20150001607 - LEE; Donovan ;   et al.
2015-01-01
Method Of Forming An Active Area With Floating Gate Negative Offset Profile In Fg Nand Memory
App 20140367762 - Tian; Ming ;   et al.
2014-12-18
Memory Device With Control Gate Oxygen Diffusion Control And Method Of Making Thereof
App 20140346584 - Purayath; Vinod R. ;   et al.
2014-11-27
Inverted-t Word Line And Formation For Non-volatile Storage
App 20140346583 - Purayath; Vinod R. ;   et al.
2014-11-27
Select gate formation for nanodot flat cell
Grant 8,823,075 - Purayath , et al. September 2, 2
2014-09-02
NAND memory device containing nanodots and method of making thereof
Grant 8,822,288 - Purayath , et al. September 2, 2
2014-09-02
Method For Using Nanoparticles To Make Uniform Discrete Floating Gate Layer
App 20140239365 - Lee; Donovan ;   et al.
2014-08-28
Three Dimensional Nand Device With Silicide Containing Floating Gates And Method Of Making Thereof
App 20140175530 - Chien; Henry ;   et al.
2014-06-26
Select Gate Formation for Nanodot Flat Cell
App 20140151778 - Purayath; Vinod ;   et al.
2014-06-05
Memory cell with resistance-switching layers
Grant 8,737,111 - Kreupl , et al. May 27, 2
2014-05-27
Non-Volatile Memory Structure Containing Nanodots and Continuous Metal Layer Charge Traps and Method of Making Thereof
App 20140001535 - Purayath; Vinod ;   et al.
2014-01-02
NAND Memory Device Containing Nanodots and Method of Making Thereof
App 20140001533 - Purayath; Vinod ;   et al.
2014-01-02
Enhanced endpoint detection in non-volatile memory fabrication processes
Grant 8,546,152 - Orimoto , et al. October 1, 2
2013-10-01
Composition of memory cell with resistance-switching layers
Grant 8,520,424 - Kreupl , et al. August 27, 2
2013-08-27
Ultrahigh density vertical NAND memory device and method of making thereof
Grant 8,461,641 - Alsmeier , et al. June 11, 2
2013-06-11
Stacked metal fin cell
Grant 8,455,939 - Alsmeier , et al. June 4, 2
2013-06-04
Ultrahigh Density Vertical Nand Memory Device And Method Of Making Thereof
App 20130069138 - Alsmeier; Johann ;   et al.
2013-03-21
Ultrahigh density monolithic three dimensional vertical NAND string memory device and method of making thereof
Grant 8,330,208 - Alsmeier , et al. December 11, 2
2012-12-11
Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer
Grant 8,263,465 - Purayath , et al. September 11, 2
2012-09-11
Ultrahigh Density Vertical Nand Memory Device And Method Of Making Thereof
App 20120199898 - Alsmeier; Johann ;   et al.
2012-08-09
Damascene method of making a nonvolatile memory device
Grant 8,222,091 - Purayath , et al. July 17, 2
2012-07-17
Stacked Metal Fin Cell
App 20120153376 - Alsmeier; Johann ;   et al.
2012-06-21
Method of forming memory with floating gates including self-aligned metal nanodots using a polymer solution
Grant 8,193,055 - Purayath , et al. June 5, 2
2012-06-05
Ultrahigh density vertical NAND memory device and method of making thereof
Grant 8,187,936 - Alsmeier , et al. May 29, 2
2012-05-29
Damascene Method Of Making A Nonvolatile Memory Device
App 20120077318 - PURAYATH; Vinod Robert ;   et al.
2012-03-29
Methods of forming high density semiconductor devices using recursive spacer technique
Grant 8,143,156 - Matamis , et al. March 27, 2
2012-03-27
Damascene method of making a nonvolatile memory device
Grant 8,097,498 - Purayath , et al. January 17, 2
2012-01-17
Ultrahigh Density Vertical Nand Memory Device And Method Of Making Thereof
App 20120001252 - Alsmeier; Johann ;   et al.
2012-01-05
Non-Volatile Memory With Flat Cell Structures And Air Gap Isolation
App 20110309430 - Purayath; Vinod Robert ;   et al.
2011-12-22
Composition Of Memory Cell With Resistance-Switching Layers
App 20110310655 - Kreupl; Franz ;   et al.
2011-12-22
Memory Cell With Resistance-Switching Layers
App 20110310653 - Kreupl; Franz ;   et al.
2011-12-22
Methods of forming NAND flash memory with fixed charge
Grant 8,030,160 - Orimoto , et al. October 4, 2
2011-10-04
Non-volatile Memory Cell Containing Nanodots And Method Of Making Thereof
App 20110186799 - Kai; James ;   et al.
2011-08-04
Damascene Method Of Making A Nonvolatile Memory Device
App 20110183475 - PURAYATH; Vinod Robert ;   et al.
2011-07-28
Spacer patterns using assist layer for high density semiconductor devices
Grant 7,960,266 - Kai , et al. June 14, 2
2011-06-14
Composite charge storage structure formation in non-volatile memory using etch stop technologies
Grant 7,939,407 - Purayath , et al. May 10, 2
2011-05-10
Non-volatile memory with sidewall channels and raised source/drain regions
Grant 7,915,664 - Chien , et al. March 29, 2
2011-03-29
Non-volatile memory fabrication and isolation for composite charge storage structures
Grant 7,888,210 - Purayath , et al. February 15, 2
2011-02-15
Lithographically space-defined charge storage regions in non-volatile memory
Grant 7,807,529 - Purayath , et al. October 5, 2
2010-10-05
Spacer Patterns Using Assist Layer For High Density Semiconductor Devices
App 20100240182 - Kai; James ;   et al.
2010-09-23
Methods of forming integrated circuit devices using composite spacer structures
Grant 7,795,080 - Orimoto , et al. September 14, 2
2010-09-14
Spacer patterns using assist layer for high density semiconductor devices
Grant 7,773,403 - Kai , et al. August 10, 2
2010-08-10
Method Of Forming Memory With Floating Gates Including Self-aligned Metal Nanodots Using A Coupling Layer
App 20100190319 - Purayath; Vinod Robert ;   et al.
2010-07-29
Methods Of Forming Nand Flash Memory With Fixed Charge
App 20100178742 - Orimoto; Takashi ;   et al.
2010-07-15
Non-volatile memory arrays having dual control gate cell structures and a thick control gate dielectric and methods of forming
Grant 7,736,973 - Orimoto , et al. June 15, 2
2010-06-15
Methods of forming NAND flash memory with fixed charge
Grant 7,732,275 - Orimoto , et al. June 8, 2
2010-06-08
Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer
Grant 7,723,186 - Purayath , et al. May 25, 2
2010-05-25
Integrated non-volatile memory and peripheral circuitry fabrication
Grant 7,704,832 - Kai , et al. April 27, 2
2010-04-27
Composite Charge Storage Structure Formation In Non-Volatile Memory Using Etch Stop Technologies
App 20100055889 - Purayath; Vinod Robert ;   et al.
2010-03-04
NAND flash memory with fixed charge
Grant 7,619,926 - Orimoto , et al. November 17, 2
2009-11-17
Composite charge storage structure formation in non-volatile memory using etch stop technologies
Grant 7,615,447 - Purayath , et al. November 10, 2
2009-11-10
Non-volatile Memory With Sidewall Channels And Raised Source/drain Regions
App 20090261398 - Chien; Henry ;   et al.
2009-10-22
Methods of forming spacer patterns using assist layer for high density semiconductor devices
Grant 7,592,225 - Kai , et al. September 22, 2
2009-09-22
Methods of fabricating non-volatile memory with integrated select and peripheral circuitry and post-isolation memory cell formation
Grant 7,592,223 - Pham , et al. September 22, 2
2009-09-22
Methods of fabricating non-volatile memory with integrated peripheral circuitry and pre-isolation memory cell formation
Grant 7,582,529 - Matamis , et al. September 1, 2
2009-09-01
Non-Volatile Memory Arrays Having Dual Control Gate Cell Structures And A Thick Control Gate Dielectric And Methods Of Forming
App 20090189211 - Orimoto; Takashi ;   et al.
2009-07-30
Lithographically Space-Defined Charge Storage Regions In Non-Volatile Memory
App 20090163008 - Purayath; Vinod Robert ;   et al.
2009-06-25
Composite Charge Storage Structure Formation In Non-Volatile Memory Using Etch Stop Technologies
App 20090163009 - Purayath; Vinod Robert ;   et al.
2009-06-25
Enhanced Endpoint Detection In Non-Volatile Memory Fabrication Processes
App 20090162951 - Orimoto; Takashi ;   et al.
2009-06-25
Non-Volatile Memory Fabrication And Isolation For Composite Charge Storage Structures
App 20090162977 - Purayath; Vinod Robert ;   et al.
2009-06-25
Method Of Forming Memory With Floating Gates Including Self-aligned Metal Nanodots Using A Coupling Layer
App 20090155967 - Purayath; Vinod Robert ;   et al.
2009-06-18
Floating Gate With Universal Etch Stop Layer
App 20090147576 - Matamis; George ;   et al.
2009-06-11
Methods of forming NAND memory with virtual channel
Grant 7,494,870 - Chien , et al. February 24, 2
2009-02-24
NAND memory with virtual channel
Grant 7,495,282 - Orimoto , et al. February 24, 2
2009-02-24
Methods Of Forming High Density Semiconductor Devices Using Recursive Spacer Technique
App 20080318381 - Matamis; George ;   et al.
2008-12-25
Methods Of Fabricating Non-Volatile Memory With Integrated Select And Peripheral Circuitry And Post-Isolation Memory Cell Formation
App 20080268596 - Pham; Tuan ;   et al.
2008-10-30
Integrated Non-Volatile Memory And Peripheral Circuitry Fabrication
App 20080248621 - Kai; James ;   et al.
2008-10-09
Methods Of Fabricating Non-Volatile Memory With Integrated Peripheral Circuitry And Pre-Isolation Memory Cell Formation
App 20080248622 - Matamis; George ;   et al.
2008-10-09
Nand Flash Memory With Fixed Charge
App 20080239819 - Orimoto; Takashi ;   et al.
2008-10-02
Methods Of Forming Nand Flash Memory With Fixed Charge
App 20080242006 - Orimoto; Takashi ;   et al.
2008-10-02
NAND Memory with Virtual Channel
App 20080170438 - Orimoto; Takashi ;   et al.
2008-07-17
Spacer Patterns Using Assist Layer for High Density Semiconductor Devices
App 20080169567 - Kai; James ;   et al.
2008-07-17
Methods Of Forming Integrated Circuit Devices Using Composite Spacer Structures
App 20080171406 - Orimoto; Takashi ;   et al.
2008-07-17
Methods of Forming NAND Memory with Virtual Channel
App 20080171415 - Chien; Henry ;   et al.
2008-07-17
Methods of Forming Spacer Patterns Using Assist Layer For High Density Semiconductor Devices
App 20080171428 - Kai; James ;   et al.
2008-07-17
Method for forming inlaid structures for IC interconnections
Grant 7,279,410 - Okada , et al. October 9, 2
2007-10-09
Method for forming dual inlaid structures for IC interconnections
Grant 6,767,827 - Okada , et al. July 27, 2
2004-07-27

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed