Kageshima; Atsushi

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kageshima; Atsushi.The latest application filed is for "semiconductor integrated circuit simulation apparatus and simulation method for semiconductor integrated circuit".

Company Profile

0.8.4

Kageshima; Atsushi - Yokohama N/A JP
KAGESHIMA; Atsushi - Kanagawa JP
KAGESHIMA; Atsushi - Yokohama-Shi JP
Kageshima; Atsushi - Tokyo JP
Kageshima; Atsushi - Kanagawa-ken JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Architecture verifying apparatus, method for verifying architecture, and computer readable medium comprising computer program code for verifying architecture Grant 8,356,195 - Kageshima January 15, 2	2013-01-15
Semiconductor Integrated Circuit Simulation Apparatus And Simulation Method For Semiconductor Integrated Circuit App 20120245915 - KAGESHIMA; Atsushi	2012-09-27
Architecture Verifying Apparatus, Method For Verifying Architecture, And Computer Readable Medium Comprising Computer Program Code For Verifying Architecture App 20100313047 - KAGESHIMA; Atsushi	2010-12-09
Architecture Verifying Apparatus, Architecture Verifying Method, And Medium Storing Architecture Verifying Program App 20100088451 - Kageshima; Atsushi	2010-04-08
Debugging Method Grant 7,093,165 - Kageshima August 15, 2	2006-08-15
Software debugger, system-level debugger, debugging method, and debugging program App 20030097613 - Kageshima, Atsushi	2003-05-22
Processor power consumption estimating system, processor power consumption estimating method, and storage medium storing program for executing the processor power consumption estimating method Grant 6,205,555 - Kageshima , et al. March 20, 2	2001-03-20
Power simulation system, power simulation method and computer-readable recording medium for recording power simulation program Grant 6,096,089 - Kageshima August 1, 2	2000-08-01
Power estimation of a microprocessor based on power consumption of memory Grant 6,055,640 - Kageshima , et al. April 25, 2	2000-04-25
Method of estimating power consumption of each instruction processed by a microprocessor Grant 5,941,991 - Kageshima August 24, 1	1999-08-24
Parallel simulator for semiconductor integrated circuit Grant 5,784,591 - Kageshima July 21, 1	1998-07-21

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