Kadiyala; Suresh

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kadiyala; Suresh.The latest application filed is for "intelligent architecture creator".

Company Profile

0.18.16

Kadiyala; Suresh - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Intelligent Architecture Creator App 20140082325 - Pandurangan; Anand ; et al.	2014-03-20
Automatic optimal integrated circuit generator from algorithms and specification App 20130346926 - Pandurangan; Anand ; et al.	2013-12-26
Application driven power gating Grant 8,589,854 - Ng , et al. November 19, 2	2013-11-19
Programmatic auto-convergent method for "physical layout power hot-spot" risk aware ASIP architecture customization for performance optimization Grant 8,572,544 - Durbha , et al. October 29, 2	2013-10-29
Programmatic auto-convergent method for physical design floorplan aware re-targetable tool suite generation (compiler-in-the-loop) for simultaneous instruction level (software) power optimization and architecture level performance optimization for ASIP design Grant 8,561,005 - Durbha , et al. October 15, 2	2013-10-15
Direct hardware processing of internal data structure fields Grant 8,555,260 - Kizhepat , et al. October 8, 2	2013-10-08
Automatic Optimal Integrated Circuit Generator From Algorithms And Specification App 20130263067 - Padmanabhan; Satish ; et al.	2013-10-03
System, architecture and micro-architecture (SAMA) representation of an integrated circuit Grant 8,484,588 - Ng , et al. July 9, 2	2013-07-09
Programmatic Auto-convergent Method For Physical Design Floorplan Aware Re-targetable Tool Suite Generation (compiler-in-the-loop) For Simultaneous Instruction Level (software) Power Optimization And Architecture Level Performance Optimization For Asip Design App 20130111426 - Durbha; Ananth ; et al.	2013-05-02
Programmatic Auto-convergent Method For "physical Layout Power Hot-spot" Risk Aware Asip Architecture Customization For Performance Optimization App 20130104097 - Durbha; Ananth ; et al.	2013-04-25
Intelligent architecture creator Grant 8,423,929 - Pandurangan , et al. April 16, 2	2013-04-16
Automatic optimal integrated circuit generator from algorithms and specification Grant 8,370,784 - Padmanabhan , et al. February 5, 2	2013-02-05
Architecture optimizer Grant 8,336,017 - Kadiyala , et al. December 18, 2	2012-12-18
Architecture Optimizer App 20120185809 - Kadiyala; Suresh ; et al.	2012-07-19
Tool Generator App 20120185820 - Kadiyala; Suresh ; et al.	2012-07-19
Automatic optimal integrated circuit generator from algorithms and specification Grant 8,225,247 - Padmanabhan , et al. July 17, 2	2012-07-17
Architectural level power-aware optimization and risk mitigation Grant 8,185,862 - Durbha , et al. May 22, 2	2012-05-22
Intelligent Architecture Creator App 20120096420 - Pandurangan; Anand ; et al.	2012-04-19
Automatic Optimal Integrated Circuit Generator From Algorithms And Specification App 20120017187 - Padmanabhan; Satish ; et al.	2012-01-19
System, Architecture And Micro-architecture (sama) Representation Of An Integrated Circuit App 20120017196 - Ng; Plus ; et al.	2012-01-19
Application Driven Power Gating App 20120017198 - Ng; Pius ; et al.	2012-01-19
Automatic Optimal Integrated Circuit Generator From Algorithms And Specification App 20120017185 - Padmanabhan; Satish ; et al.	2012-01-19
Architectural Level Power-aware Optimization And Risk Mitigation App 20120017189 - Durbha; Ananth ; et al.	2012-01-19
Direct hardware processing of internal data structure fields Grant 7,493,481 - Kizhepat , et al. February 17, 2	2009-02-17

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