| Patent | Date |
|---|
Image sensor having separate, stacked, pixel array, DRAM, and logic/analog-digital converter integrated circuit die
Grant 10,834,347 - Jung , et al. November 10, 2 | 2020-11-10 |
Configurable interface alignment buffer between DRAM and logic unit for multiple-wafer image sensors
Grant 10,834,352 - Qin , et al. November 10, 2 | 2020-11-10 |
Configurable Interface Alignment Buffer Between Dram And Logic Unit For Multiple-wafer Image Sensors
App 20200228739 - QIN; Qing ; et al. | 2020-07-16 |
Fast Access Dram With 2 Cell-per-bit, Common Word Line, Architecture
App 20200105336 - JUNG; Taehyung ; et al. | 2020-04-02 |
Image Sensor Having Separate, Stacked, Pixel Array, Dram, And Logic/analog-digital Converter Integrated Circuit Die
App 20200092509 - JUNG; Taehyung ; et al. | 2020-03-19 |
Multiport memory architecture for simultaneous transfer
Grant 10,360,952 - Jung , et al. | 2019-07-23 |
Memory with pattern oriented error correction code
Grant 10,289,486 - Ryu , et al. | 2019-05-14 |
DRAM core architecture with wide I/Os
Grant 10,255,968 - Na , et al. | 2019-04-09 |
Dram Core Architecture With Wide I/os
App 20190027209 - Na; Jongsik ; et al. | 2019-01-24 |
Memory With Pattern Oriented Error Correction Code
App 20190018732 - Ryu; Hoon ; et al. | 2019-01-17 |
Multiport Memory Architecture
App 20180173456 - Jung; Taehyung ; et al. | 2018-06-21 |
Semiconductor device and semiconductor memory device
Grant 9,728,235 - Jung , et al. August 8, 2 | 2017-08-08 |
Oscillator circuit with location-based charge pump enable and semiconductor memory including the same
Grant 9,093,167 - Jung July 28, 2 | 2015-07-28 |
Wordline coupling reduction technique
Grant 8,902,676 - Jung , et al. December 2, 2 | 2014-12-02 |
Storage cell bridge screen technique
Grant 8,861,294 - Jung , et al. October 14, 2 | 2014-10-14 |
Oscillator Circuit With Location-Based Charge Pump Enable And Semiconductor Memory Including The Same
App 20140146608 - Jung; TaeHyung | 2014-05-29 |
Semiconductor memory device
Grant 8,644,089 - Jung February 4, 2 | 2014-02-04 |
Semiconductor Device And Semiconductor Memory Device
App 20140022856 - JUNG; Taehyung ; et al. | 2014-01-23 |
Storage Cell Bridge Screen Technique
App 20140003175 - Jung; TaeHyung ; et al. | 2014-01-02 |
Semiconductor Memory Device
App 20130336073 - JUNG; Taehyung | 2013-12-19 |
Wordline Coupling Reduction Technique
App 20130286754 - Jung; TaeHyung ; et al. | 2013-10-31 |
Memory circuits, systems, and methods for providing bit line equalization voltages
Grant 8,279,686 - Hsu , et al. October 2, 2 | 2012-10-02 |
Memory Circuits, Systems, And Methods For Providing Bit Line Equalization Voltages
App 20100202220 - HSU; Kuoyuan Peter ; et al. | 2010-08-12 |
Circuit and method for a gate control circuit with reduced voltage stress
Grant 7,592,858 - Jung September 22, 2 | 2009-09-22 |
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