| Patent | Date |
|---|
Microelectronic Assemblies
App 20220278057 - Elsherbini; Adel A. ; et al. | 2022-09-01 |
Metallization structures for stacked device connectivity and their methods of fabrication
Grant 11,430,814 - Lilak , et al. August 30, 2 | 2022-08-30 |
Microelectronic Assemblies
App 20220254754 - ELSHERBINI; Adel A. ; et al. | 2022-08-11 |
Stacked transistors with Si PMOS and high mobility thin film transistor NMOS
Grant 11,393,818 - Dewey , et al. July 19, 2 | 2022-07-19 |
Microelectronic assemblies
Grant 11,393,777 - Elsherbini , et al. July 19, 2 | 2022-07-19 |
Self-aligned Interconnect Structures And Methods Of Fabrication
App 20220199468 - Jun; Kimin ; et al. | 2022-06-23 |
Shield Structures In Microelectronic Assemblies Having Direct Bonding
App 20220199546 - Elsherbini; Adel A. ; et al. | 2022-06-23 |
Microelectronic assemblies
Grant 11,348,897 - Elsherbini , et al. May 31, 2 | 2022-05-31 |
Wrap-around Source/drain Method Of Making Contacts For Backside Metals
App 20220140127 - MORROW; Patrick ; et al. | 2022-05-05 |
Wrap-around Source/drain Method Of Making Contacts For Backside Metals
App 20220140128 - MORROW; Patrick ; et al. | 2022-05-05 |
Fabrication And Use Of Through Silicon Vias On Double Sided Interconnect Device
App 20220130803 - MUELLER; Brennen K. ; et al. | 2022-04-28 |
Direct Bonding In Microelectronic Assemblies
App 20220093492 - Elsherbini; Adel A. ; et al. | 2022-03-24 |
3d Heterogeneous Integrated Crystalline Piezoelectric Bulk Acoustic Resonators
App 20220093683 - THEN; Han Wui ; et al. | 2022-03-24 |
Three-dimensional Integrated Circuits (3dics) Including Bottom Gate Mos Transistors With Monocrystalline Channel Material
App 20220093586 - Huang; Cheng-Ying ; et al. | 2022-03-24 |
Microelectronic Assemblies With Inductors In Direct Bonding Regions
App 20220093547 - Elsherbini; Adel A. ; et al. | 2022-03-24 |
Capacitors And Resistors At Direct Bonding Interfaces In Microelectronic Assemblies
App 20220093725 - Elsherbini; Adel A. ; et al. | 2022-03-24 |
Monolithic Chip Stacking Using A Die With Double-sided Interconnect Layers
App 20220093569 - Pancholi; Anup ; et al. | 2022-03-24 |
Microelectronic Assemblies With Inductors In Direct Bonding Regions
App 20220093546 - Elsherbini; Adel A. ; et al. | 2022-03-24 |
Backside Contact Structures And Fabrication For Metal On Both Sides Of Devices
App 20220069094 - MORROW; Patrick ; et al. | 2022-03-03 |
Wrap-around source/drain method of making contacts for backside metals
Grant 11,264,493 - Morrow , et al. March 1, 2 | 2022-03-01 |
Monolithic chip stacking using a die with double-sided interconnect layers
Grant 11,251,158 - Pancholi , et al. February 15, 2 | 2022-02-15 |
Fabrication and use of through silicon vias on double sided interconnect device
Grant 11,251,156 - Mueller , et al. February 15, 2 | 2022-02-15 |
Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material
Grant 11,244,943 - Huang , et al. February 8, 2 | 2022-02-08 |
Gate-all-around Integrated Circuit Structures Having Strained Dual Nanoribbon Channel Structures
App 20210407996 - AGRAWAL; Ashish ; et al. | 2021-12-30 |
Backside contact structures and fabrication for metal on both sides of devices
Grant 11,201,221 - Morrow , et al. December 14, 2 | 2021-12-14 |
Resonator structure encapsulation
Grant 11,121,691 - Lin , et al. September 14, 2 | 2021-09-14 |
Three-dimensional Integrated Circuits (3dics) Including Bottom Gate Mos Transistors With Monocrystalline Channel Material
App 20210202476 - Huang; Cheng-Ying ; et al. | 2021-07-01 |
Integrated Circuit Device Structures And Double-sided Electrical Testing
App 20210175124 - RAO; Valluri R. ; et al. | 2021-06-10 |
Techniques For Revealing A Backside Of An Integrated Circuit Device, And Associated Configurations
App 20210104435 - SON; Il-Seok ; et al. | 2021-04-08 |
Stacked Transistors With Si Pmos And High Mobility Thin Film Transistor Nmos
App 20210091080 - DEWEY; Gilbert ; et al. | 2021-03-25 |
Iii-v Source/drain In Top Nmos Transistors For Low Temperature Stacked Transistor Contacts
App 20210057413 - DEWEY; Gilbert ; et al. | 2021-02-25 |
Techniques for revealing a backside of an integrated circuit device, and associated configurations
Grant 10,896,847 - Son , et al. January 19, 2 | 2021-01-19 |
Integrated circuit structures
Grant 10,872,820 - Block , et al. December 22, 2 | 2020-12-22 |
Metallization Structures For Stacked Device Connectivity And Their Methods Of Fabrication
App 20200395386 - Lilak; Aaron D. ; et al. | 2020-12-17 |
Backside Contact Structures And Fabrication For Metal On Both Sides Of Devices
App 20200381525 - MORROW; Patrick ; et al. | 2020-12-03 |
Methods of forming backside self-aligned vias and structures formed thereby
Grant 10,797,139 - Morrow , et al. October 6, 2 | 2020-10-06 |
Backside contact structures and fabrication for metal on both sides of devices
Grant 10,784,358 - Morrow , et al. Sept | 2020-09-22 |
Stacked Transistors Having Device Strata With Different Channel Widths
App 20200295003 - Dewey; Gilbert W. ; et al. | 2020-09-17 |
Multi-layer silicon/gallium nitride semiconductor
Grant 10,763,248 - Dasgupta , et al. Sep | 2020-09-01 |
Microelectronic Assemblies
App 20200273839 - ELSHERBINI; Adel A. ; et al. | 2020-08-27 |
Stacked Transistors With Dielectric Between Channels Of Different Device Strata
App 20200266218 - Lilak; Aaron D. ; et al. | 2020-08-20 |
Microelectronic Assemblies
App 20200235061 - Elsherbini; Adel A. ; et al. | 2020-07-23 |
Multi-layer Silicon/gallium Nitride Semiconductor
App 20200227396 - DASGUPTA; Sansaptak W. ; et al. | 2020-07-16 |
Self-aligned Stacked Ge/si Cmos Transistor Structure
App 20200212038 - RACHMADY; Willy ; et al. | 2020-07-02 |
Three Dimensional Integrated Circuits With Stacked Transistors
App 20200211905 - HUANG; Cheng-Ying ; et al. | 2020-07-02 |
Monolithic Chip Stacking Using A Die With Double-sided Interconnect Layers
App 20200212011 - Pancholi; Anup ; et al. | 2020-07-02 |
Silicon die with integrated high voltage devices
Grant 10,700,039 - Nelson , et al. | 2020-06-30 |
Transistors On Heterogeneous Bonding Layers
App 20200194570 - Jun; Kimin ; et al. | 2020-06-18 |
Vertical Memory Cells
App 20200194435 - LILAK; Aaron ; et al. | 2020-06-18 |
Metal on both sides with clock gated-power and signal routing underneath
Grant 10,658,291 - Nelson , et al. | 2020-05-19 |
Vertically Stacked Cmos With Upfront M0 Interconnect
App 20200098921 - RACHMADY; Willy ; et al. | 2020-03-26 |
Integrated Circuit Device Structures And Double-sided Fabrication Techniques
App 20200035560 - BLOCK; Bruce ; et al. | 2020-01-30 |
Heterogeneous integration of ultrathin functional block by solid phase adhesive and selective transfer
Grant 10,522,510 - Jun , et al. Dec | 2019-12-31 |
Techniques For Revealing A Backside Of An Integrated Circuit Device, And Associated Configurations
App 20190371666 - SON; Il-Seok ; et al. | 2019-12-05 |
Techniques for revealing a backside of an integrated circuit device, and associated configurations
Grant 10,490,449 - Son , et al. Nov | 2019-11-26 |
Methods Of Forming Backside Self-aligned Vias And Structures Formed Thereby
App 20190326405 - Morrow; Patrick ; et al. | 2019-10-24 |
Methods and devices integrating III-N transistor circuitry with Si transistor circuitry
Grant 10,453,679 - Dasgupta , et al. Oc | 2019-10-22 |
Multi-gate high electron mobility transistors and methods of fabrication
Grant 10,439,057 - Jun , et al. O | 2019-10-08 |
Resonator Structure Encapsulation
App 20190267961 - LIN; Kevin ; et al. | 2019-08-29 |
Methods of forming backside self-aligned vias and structures formed thereby
Grant 10,367,070 - Morrow , et al. July 30, 2 | 2019-07-30 |
Vertical channel transistors fabrication process by selective subtraction of a regular grid
Grant 10,361,090 - Jun , et al. | 2019-07-23 |
Monolithic three-dimensional (3D) ICs with local inter-level interconnects
Grant 10,297,592 - Morrow , et al. | 2019-05-21 |
Metal On Both Sides With Clock Gated-power And Signal Routing Underneath
App 20190122985 - NELSON; Donald W. ; et al. | 2019-04-25 |
Partial layer transfer system and method
Grant 10,236,282 - Morrow , et al. | 2019-03-19 |
Permanent Functional Carrier Systems And Methods
App 20190057950 - Mueller; Brennen K. ; et al. | 2019-02-21 |
Metal on both sides with clock gated-power and signal routing underneath
Grant 10,186,484 - Nelson , et al. Ja | 2019-01-22 |
Methods And Devices Integrating Iii-n Transistor Circuitry With Si Transistor Circuitry
App 20190006171 - Dasgupta; Sansaptak ; et al. | 2019-01-03 |
Fabrication And Use Of Through Silicon Vias On Double Sided Interconnect Device
App 20180323174 - MUELLER; Brennen K. ; et al. | 2018-11-08 |
Method for direct integration of memory die to logic die without use of thru silicon vias (TSV)
Grant 10,068,874 - Nelson , et al. September 4, 2 | 2018-09-04 |
Methods Of Forming Backside Self-aligned Vias And Structures Formed Thereby
App 20180248012 - Morrow; Patrick ; et al. | 2018-08-30 |
Techniques For Revealing A Backside Of An Integrated Circuit Device, And Associated Configurations
App 20180233409 - SON; Il-Seok ; et al. | 2018-08-16 |
Techniques for forming vertical transistor architectures
Grant 10,043,797 - Jun , et al. August 7, 2 | 2018-08-07 |
Wrap-around Source/drain Method Of Making Contacts For Backside Metals
App 20180219090 - MORROW; Patrick ; et al. | 2018-08-02 |
Backside Contact Structures And Fabrication For Metal On Both Sides Of Devices
App 20180219075 - MORROW; Patrick ; et al. | 2018-08-02 |
Planar heterogeneous device
Grant 10,014,374 - Jun , et al. July 3, 2 | 2018-07-03 |
Heterogeneous Integration Of Ultrathin Functional Block By Solid Phase Adhesive And Selective Transfer
App 20180151541 - JUN; Kimin ; et al. | 2018-05-31 |
High electron mobility transistor fabrication process on reverse polarized substrate by layer transfer
Grant 9,935,191 - Jun , et al. April 3, 2 | 2018-04-03 |
Methods and apparatus for ultrathin catalyst layer for photoelectrode
Grant 9,920,438 - Jun , et al. March 20, 2 | 2018-03-20 |
Liquid metal interconnects
Grant 9,835,648 - Baskaran , et al. December 5, 2 | 2017-12-05 |
Methods of forming buried vertical capacitors and structures formed thereby
Grant 9,818,751 - Baskaran , et al. November 14, 2 | 2017-11-14 |
MONOLITHIC THREE-DIMENSIONAL (3D) ICs WITH LOCAL INTER-LEVEL INTERCONNECTS
App 20170287905 - Morrow; Patrick ; et al. | 2017-10-05 |
Multi-gate High Electron Mobility Transistors And Methods Of Fabrication
App 20170229565 - JUN; Kimin ; et al. | 2017-08-10 |
Methods Of Forming Buried Vertical Capacitors And Structures Formed Thereby
App 20170221901 - Baskaran; Rajashree ; et al. | 2017-08-03 |
Methods of forming under device interconnect structures
Grant 9,721,898 - Morrow , et al. August 1, 2 | 2017-08-01 |
Monolithic three-dimensional (3D) ICs with local inter-level interconnects
Grant 9,685,436 - Morrow , et al. June 20, 2 | 2017-06-20 |
Methods of forming buried vertical capacitors and structures formed thereby
Grant 9,646,972 - Baskaran , et al. May 9, 2 | 2017-05-09 |
High Electron Mobility Transistor Fabrication Process On Reverse Polarized Substrate By Layer Transfer
App 20170077281 - JUN; Kimin ; et al. | 2017-03-16 |
Embedded Memory In Interconnect Stack On Silicon Die
App 20170077389 - NELSON; Donald W. ; et al. | 2017-03-16 |
Metal On Both Sides With Clock Gated-power And Signal Routing Underneath
App 20170077030 - NELSON; Donald W. ; et al. | 2017-03-16 |
Silicon Die With Integrated High Voltage Devices
App 20170069597 - NELSON; Donald W. ; et al. | 2017-03-09 |
Method For Direct Integration Of Memory Die To Logic Die Without Use Of Thru Silicon Vias (tsv)
App 20170069598 - NELSON; Donald W. ; et al. | 2017-03-09 |
Heterogeneous layer device
Grant 9,590,051 - Jun , et al. March 7, 2 | 2017-03-07 |
Surface Encapsulation For Wafer Bonding
App 20170062569 - JUN; Kimin ; et al. | 2017-03-02 |
Methods Of Forming Under Device Interconnect Structures
App 20170025355 - Morrow; Patrick ; et al. | 2017-01-26 |
Techniques For Forming Vertical Transistor Architectures
App 20170025412 - JUN; KIMIN ; et al. | 2017-01-26 |
Heterogeneous semiconductor material integration techniques
Grant 9,548,320 - Levander , et al. January 17, 2 | 2017-01-17 |
Vertical Channel Transistors Fabrication Process By Selective Subtraction Of A Regular Grid
App 20170011929 - JUN; Kimin ; et al. | 2017-01-12 |
Methods of forming under device interconnect structures
Grant 9,490,201 - Morrow , et al. November 8, 2 | 2016-11-08 |
Heterogeneous Layer Device
App 20160247887 - JUN; KIMIN ; et al. | 2016-08-25 |
Planar Heterogeneous Device
App 20160247882 - JUN; KIMIN ; et al. | 2016-08-25 |
Partial Layer Transfer System And Method
App 20160233206 - MORROW; PATRICK ; et al. | 2016-08-11 |
Methods Of Forming Buried Vertical Capacitors And Structures Formed Thereby
App 20160204110 - Baskaran; Rajashree ; et al. | 2016-07-14 |
MONOLITHIC THREE-DIMENSIONAL (3D) ICs WITH LOCAL INTER-LEVEL INTERCONNECTS
App 20160197069 - Morrow; Patrick ; et al. | 2016-07-07 |
Heterogeneous Semiconductor Material Integration Techniques
App 20160056180 - LEVANDER; ALEJANDRO X. ; et al. | 2016-02-25 |
Heterogeneous semiconductor material integration techniques
Grant 9,177,967 - Levander , et al. November 3, 2 | 2015-11-03 |
Heterogeneous Semiconductor Material Integration Techniques
App 20150179664 - Levander; Alejandro X. ; et al. | 2015-06-25 |
Methods Of Forming Under Device Interconnect Structures
App 20140264739 - Morrow; Patrick ; et al. | 2014-09-18 |
Methods and Apparatus for Ultrathin Catalyst Layer for Photoelectrode
App 20130008495 - Jun; Kimin ; et al. | 2013-01-10 |
Liquid Metal Interconnects
App 20130000117 - Baskaran; Rajashree ; et al. | 2013-01-03 |
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