Juengling; Werner

Patent Applications and Registrations

Patent applications and USPTO patent grants for Juengling; Werner.The latest application filed is for "memory circuitry and methods of forming memory circuitry".

Company Profile

6.200.188

Juengling; Werner - Meridian ID
Juengling; Werner - Boise ID
Juengling; Werner - Saratoga Springs NY
- Boise ID US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated assemblies comprising vertically-stacked decks Grant 11,410,980 - Juengling August 9, 2	2022-08-09
Integrated assemblies Grant 11,348,871 - Juengling May 31, 2	2022-05-31
Memory Circuitry And Methods Of Forming Memory Circuitry App 20210134815 - Juengling; Werner	2021-05-06
Methods used in forming an array of memory cells Grant 10,978,484 - Juengling April 13, 2	2021-04-13
Integrated Assemblies Comprising Vertically-Stacked Decks App 20210050338 - Juengling; Werner	2021-02-18
FinFETs with deposited fin bodies Grant 10,892,349 - Juengling January 12, 2	2021-01-12
Memory circuitry and methods of forming memory circuitry Grant 10,886,285 - Juengling January 5, 2	2021-01-05
Memory circuitry having a pair of immediately-adjacent memory arrays having space laterally-there-between that has a conductive interconnect in the space Grant 10,872,894 - Juengling December 22, 2	2020-12-22
Integrated Assemblies Having Body Contact Regions Proximate Transistor Body Regions; and Methods Utilizing Bowl Etches During Fabrication of Integrated Assemblies App 20200381438 - Juengling; Werner	2020-12-03
Integrated assemblies comprising vertically-stacked decks of memory arrays Grant 10,833,059 - Juengling November 10, 2	2020-11-10
Integrated assemblies comprising redundant wiring routes, and integrated circuit decks having openings extending therethrough Grant 10,811,340 - Juengling October 20, 2	2020-10-20
Memory arrays comprising ferroelectric capacitors Grant 10,790,288 - Juengling September 29, 2	2020-09-29
Apparatuses including 3D memory arrays, methods of forming the apparatuses, and related electronic systems Grant 10,790,286 - Juengling September 29, 2	2020-09-29
Integrated assemblies having body contact regions proximate transistor body regions; and methods utilizing bowl etches during fabrication of integrated assemblies Grant 10,784,264 - Juengling Sept	2020-09-22
Methods Used in Forming an Array of Memory Cells App 20200243547 - Juengling; Werner	2020-07-30
Integrated Assemblies Comprising Redundant Wiring Routes, and Integrated Circuit Decks Having Openings Extending Therethrough App 20200219795 - Juengling; Werner	2020-07-09
Methods of forming memory arrays Grant 10,692,871 - Juengling	2020-06-23
Methods used in forming an array of memory cells Grant 10,692,887 - Juengling	2020-06-23
Memory Circuitry And Methods Of Forming Memory Circuitry App 20200185396 - Juengling; Werner	2020-06-11
Apparatuses Including 3d Memory Arrays, Methods Of Forming The Apparatuses, And Related Electronic Systems App 20200185385 - Juengling; Werner	2020-06-11
Integrated Assemblies Having Body Contact Regions Proximate Transistor Body Regions; and Methods Utilizing Bowl Etches During Fa App 20200185390 - Juengling; Werner	2020-06-11
Integrated Assemblies Comprising Vertically-Stacked Decks App 20200185370 - Juengling; Werner	2020-06-11
Integrated Assemblies App 20200152571 - Juengling; Werner	2020-05-14
Integrated assemblies comprising redundant wiring routes, and integrated circuit decks having openings extending therethrough Grant 10,607,923 - Juengling	2020-03-31
Memory arrays Grant 10,580,776 - Juengling	2020-03-03
Integrated assemblies having structures along a first pitch coupled with structures along a second pitch different from the first pitch, and methods of forming integrated assemblies Grant 10,566,281 - Juengling Feb	2020-02-18
FinFETs with Deposited Fin Bodies App 20200052097 - Juengling; Werner	2020-02-13
Memory arrays Grant 10,504,905 - Juengling Dec	2019-12-10
Integrated Assemblies Having Structures Along a First Pitch Coupled with Structures Along a Second Pitch Different from the Firs App 20190304908 - Juengling; Werner	2019-10-03
Memory Devices, Memory Arrays, and Methods of Forming Memory Arrays App 20190296021 - Juengling; Werner	2019-09-26
FinFETs with deposited fin bodies Grant 10,424,656 - Juengling Sept	2019-09-24
Integrated assemblies having structures along a first pitch coupled with structures along a second pitch different from the first pitch, and methods of forming integrated assemblies Grant 10,388,606 - Juengling A	2019-08-20
Integrated assemblies having structures along a first pitch coupled with structures along a second pitch different from the first pitch, and methods of forming integrated assemblies Grant 10,381,305 - Juengling A	2019-08-13
Memory devices which include memory arrays Grant 10,366,994 - Juengling July 30, 2	2019-07-30
Integrated assemblies having structures along a first pitch coupled with structures along a second pitch different from the first pitch Grant 10,361,158 - Juengling	2019-07-23
Memory Arrays App 20190221568 - Juengling; Werner	2019-07-18
Memory arrays Grant 10,319,725 - Juengling	2019-06-11
Integrated Assemblies Having Structures Along a First Pitch Coupled with Structures Along a Second Pitch Different from the First Pitch, and Methods of Forming Integrated Assemblies App 20190067192 - Juengling; Werner	2019-02-28
Memory Circuitry App 20190067288 - Juengling; Werner	2019-02-28
Methods Used In Forming An Array Of Memory Cells App 20190067303 - Juengling; Werner	2019-02-28
Integrated Assemblies Having Structures Along a First Pitch Coupled with Structures Along a Second Pitch Different from the First Pitch, and Methods of Forming Integrated Assemblies App 20190067195 - Juengling; Werner	2019-02-28
Integrated Assemblies Having Structures Along a First Pitch Coupled with Structures Along a Second Pitch Different from the First Pitch, and Methods of Forming Integrated Assemblies App 20190067193 - Juengling; Werner	2019-02-28
FinFETs with Deposited Fin Bodies App 20180337263 - Juengling; Werner	2018-11-22
Apparatuses Containing FinFETS App 20180294268 - Juengling; Werner	2018-10-11
Memory Devices which include Memory Arrays App 20180261602 - Juengling; Werner	2018-09-13
Memory Arrays App 20180247942 - Juengling; Werner	2018-08-30
Methods of forming memory arrays Grant 10,014,302 - Juengling July 3, 2	2018-07-03
Memory Arrays Comprising Ferroelectric Capacitors App 20180182764 - Juengling; Werner	2018-06-28
Methods of Forming Memory Arrays App 20180182765 - Juengling; Werner	2018-06-28
Memory Arrays App 20180182763 - Juengling; Werner	2018-06-28
Memory Devices, Memory Arrays, And Methods Of Forming Memory Arrays App 20180182761 - Juengling; Werner	2018-06-28
Memory Arrays App 20180182762 - Juengling; Werner	2018-06-28
Memory arrays Grant 10,008,504 - Juengling June 26, 2	2018-06-26
Memory devices which include memory arrays Grant 10,008,503 - Juengling June 26, 2	2018-06-26
Floating body transistors and memory arrays comprising floating body transistors Grant 9,881,923 - Juengling January 30, 2	2018-01-30
Memory arrays Grant 9,875,960 - Juengling January 23, 2	2018-01-23
Methods of forming patterns, and apparatuses comprising FinFETs Grant 9,853,027 - Juengling December 26, 2	2017-12-26
Memory arrays comprising ferroelectric capacitors Grant 9,847,337 - Juengling December 19, 2	2017-12-19
Floating body transistors and memory arrays comprising floating body transistors Grant 9,773,788 - Juengling September 26, 2	2017-09-26
Memory arrays Grant 9,773,728 - Juengling September 26, 2	2017-09-26
Double gated fin transistors and methods of fabricating and operating the same Grant 9,553,193 - Juengling January 24, 2	2017-01-24
Semiconductor device comprising a transistor gate having multiple vertically oriented sidewalls Grant 9,536,971 - Juengling January 3, 2	2017-01-03
Double gated 4F2 dram CHC cell and methods of fabricating the same Grant 9,472,461 - Juengling , et al. October 18, 2	2016-10-18
Systems and devices including multi-transistor cells and methods of using, making, and operating the same Grant 9,449,652 - Juengling September 20, 2	2016-09-20
Digit line equilibration using access devices at the edge of sub-arrays Grant 9,355,709 - Juengling May 31, 2	2016-05-31
Devices with cavity-defined gates and methods of making the same Grant 9,331,203 - Juengling May 3, 2	2016-05-03
Cross-hair cell wordline formation Grant 9,281,309 - Juengling March 8, 2	2016-03-08
Systems and devices including fin field-effect transistors each having U-shaped semiconductor fin Grant 9,190,494 - Juengling November 17, 2	2015-11-17
Vertical gated access transistor Grant 9,184,161 - Juengling November 10, 2	2015-11-10
Double trench well formation in SRAM cells Grant 9,087,733 - Juengling July 21, 2	2015-07-21
Devices including fin transistors robust to gate shorts and methods of making the same Grant 9,087,721 - Juengling July 21, 2	2015-07-21
Semiconductor Structures Providing Electrical Isolation App 20150187767 - Grisham; Paul ; et al.	2015-07-02
Fin etch and Fin replacement for FinFET integration Grant 9,054,212 - Juengling June 9, 2	2015-06-09
Semiconductor Device Comprising a Transistor Gate Having Multiple Vertically Oriented Sidewalls App 20150108566 - Juengling; Werner	2015-04-23
Combination FinFET and planar FET semiconductor device and methods of making such a device Grant 9,012,986 - Chi , et al. April 21, 2	2015-04-21
Double Trench Well Formation In Sram Cells App 20150102417 - JUENGLING; Werner	2015-04-16
Double Gated 4f2 Dram Chc Cell And Methods Of Fabricating The Same App 20150093869 - Juengling; Werner ; et al.	2015-04-02
Double gated 4F2 dram CHC cell and methods of fabricating the same Grant 8,962,401 - Juengling , et al. February 24, 2	2015-02-24
Priority based layout versus schematic (LVS) Grant 8,966,418 - Mojumder , et al. February 24, 2	2015-02-24
Double trench well formation in SRAM cells Grant 8,946,050 - Juengling February 3, 2	2015-02-03
Memory with isolation structure Grant 8,933,508 - Juengling January 13, 2	2015-01-13
Devices Including Fin Transistors Robust To Gate Shorts And Methods Of Making The Same App 20150008535 - Juengling; Werner	2015-01-08
Double gated 4F2 dram CHC cell and methods of fabricating the same Grant 8,921,899 - Juengling , et al. December 30, 2	2014-12-30
Double gated 4F2 dram CHC cell and methods of fabricating the same Grant 08921899 -	2014-12-30
Semiconductor device comprising a transistor gate having multiple vertically oriented sidewalls Grant 8,916,912 - Juengling December 23, 2	2014-12-23
Method and algorithm for random half pitched interconnect layout with constant spacing Grant 8,877,639 - Juengling November 4, 2	2014-11-04
Methods of forming a three-dimensional semiconductor device with a dual stress channel and the resulting device Grant 8,877,588 - Pham , et al. November 4, 2	2014-11-04
Devices including fin transistors robust to gate shorts and methods of making the same Grant 8,866,254 - Juengling October 21, 2	2014-10-21
Floating body cell structures, devices including same, and methods for forming same Grant 8,859,359 - Tang , et al. October 14, 2	2014-10-14
Digit Line Equilibration Using Access Devices At The Edge Of Sub-arrays App 20140293720 - Juengling; Werner	2014-10-02
Memory Device Comprising An Array Portion And A Logic Portion App 20140284672 - Juengling; Werner	2014-09-25
Floating body cell structures, devices including same, and methods for forming same Grant 8,841,715 - Tang , et al. September 23, 2	2014-09-23
Memory device with recessed construction between memory constructions Grant 8,836,023 - Juengling September 16, 2	2014-09-16
Combination Finfet And Planar Fet Semiconductor Device And Methods Of Making Such A Device App 20140252480 - Chi; Min-hwa ; et al.	2014-09-11
Integrated circuits and transistor design therefor Grant 8,829,602 - Juengling September 9, 2	2014-09-09
Vertically stacked fin transistors and methods of fabricating and operating the same Grant 8,810,310 - Juengling August 19, 2	2014-08-19
Methods Of Forming A Three-dimensional Semiconductor Device With A Dual Stress Channel And The Resulting Device App 20140225168 - Pham; Daniel T. ; et al.	2014-08-14
Combination FinFET and planar FET semiconductor device and methods of making such a device Grant 8,772,117 - Chi , et al. July 8, 2	2014-07-08
Memory device comprising an array portion and a logic portion Grant 8,772,840 - Juengling July 8, 2	2014-07-08
Devices With Cavity-defined Gates And Methods Of Making The Same App 20140183626 - Juengling; Werner	2014-07-03
Systems and Devices Including Multi-Transistor Cells and Methods of Using, Making, and Operating the Same App 20140185355 - Juengling; Werner	2014-07-03
Systems and devices including multi-gate transistors and methods of using, making, and operating the same Grant 8,759,889 - Juengling June 24, 2	2014-06-24
Digit line equilibration using access devices at the edge of sub-arrays Grant 8,760,950 - Juengling June 24, 2	2014-06-24
Hierarchical layout versus schematic (LVS) comparison with extraneous device elimination Grant 8,751,985 - Puri , et al. June 10, 2	2014-06-10
Data cells with drivers and methods of making and operating the same Grant 8,750,025 - Juengling June 10, 2	2014-06-10
Combination Finfet And Planar Fet Semiconductor Device And Methods Of Making Such A Device App 20140151807 - Chi; Min-hwa ; et al.	2014-06-05
Cross-hair cell wordline formation Grant 8,741,758 - Juengling June 3, 2	2014-06-03
Double Trench Well Formation In Sram Cells App 20140117507 - JUENGLING; Werner	2014-05-01
Fin Etch And Fin Replacement For Finfet Integration App 20140117419 - JUENGLING; Werner	2014-05-01
Vertical Gated Access Transistor App 20140077295 - Juengling; Werner	2014-03-20
Devices with cavity-defined gates and methods of making the same Grant 8,669,159 - Juengling March 11, 2	2014-03-11
Vertical transistors Grant 8,633,529 - Juengling January 21, 2	2014-01-21
Locally 2 sided CHC DRAM access transistor structure Grant 8,629,483 - Juengling January 14, 2	2014-01-14
Memory having a vertical access device Grant 8,617,953 - Juengling December 31, 2	2013-12-31
Data Cells with Drivers and Methods of Making and Operating the Same App 20130329486 - Juengling; Werner	2013-12-12
FinFET having cross-hair cells Grant 8,598,653 - Juengling December 3, 2	2013-12-03
Vertical gated access transistor Grant 8,592,898 - Juengling November 26, 2	2013-11-26
Floating Body Cell Structures, Devices Including Same, and Methods for Forming Same App 20130307042 - Tang; Sanh D. ; et al.	2013-11-21
Floating Body Cell Structures, Devices Including Same, and Methods for Forming Same App 20130309820 - Tang; Sanh D. ; et al.	2013-11-21
Cross-hair cell based floating body device Grant 8,557,656 - Juengling October 15, 2	2013-10-15
Self-aligned semiconductor trench structures Grant 8,552,526 - Juengling , et al. October 8, 2	2013-10-08
Systems and devices including multi-transistor cells and methods of using, making, and operating the same Grant 8,546,876 - Juengling October 1, 2	2013-10-01
Memory With Isolation Structure App 20130248958 - Juengling; Werner	2013-09-26
Systems And Devices Including Multi-gate Transistors And Methods Of Using, Making, And Operating The Same App 20130240967 - Juengling; Werner	2013-09-19
Data cells with drivers and methods of making and operating the same Grant 8,537,608 - Juengling September 17, 2	2013-09-17
Data cells and connections to data cells Grant 8,536,631 - Juengling September 17, 2	2013-09-17
Floating body cell structures, devices including same, and methods for forming same Grant 8,530,295 - Tang , et al. September 10, 2	2013-09-10
Floating body cell structures, devices including same, and methods for forming same Grant 8,513,722 - Tang , et al. August 20, 2	2013-08-20
FinFET alignment structures using a double trench flow Grant 8,501,607 - Juengling August 6, 2	2013-08-06
Data cells with drivers and methods of making and operating the same Grant 8,503,228 - Juengling August 6, 2	2013-08-06
Multi-level DRAM cell using CHC technology Grant 8,497,550 - Juengling July 30, 2	2013-07-30
Concentric or nested container capacitor structure for integrated circuits Grant 8,482,046 - Juengling July 9, 2	2013-07-09
Vertical Transistors App 20130140618 - Juengling; Werner	2013-06-06
Systems and devices including multi-gate transistors and methods of using, making, and operating the same Grant 8,450,785 - Juengling May 28, 2	2013-05-28
Self-aligned Semiconductor Trench Structures App 20130113069 - Juengling; Werner ; et al.	2013-05-09
Systems and devices including local data lines and methods of using, making, and operating the same Grant 8,416,610 - Juengling April 9, 2	2013-04-09
Semiconductor device comprising a transistor gate having multiple vertically oriented sidewalls Grant 8,399,920 - Juengling March 19, 2	2013-03-19
Non-planar thin fin transistor Grant 8,384,142 - Juengling February 26, 2	2013-02-26
Vertically Stacked Fin Transistors And Methods Of Fabricating And Operating The Same App 20130043531 - Juengling; Werner	2013-02-21
Vertical transistors Grant 8,372,710 - Juengling February 12, 2	2013-02-12
Cross-hair cell wordline formation Grant 8,357,601 - Juengling January 22, 2	2013-01-22
Cross-hair Cell Devices And Methods For Manufacturing The Same App 20130015521 - Juengling; Werner	2013-01-17
Floating Body Cell Structures, Devices Including Same, and Methods for Forming Same App 20130011977 - Tang; Sanh D. ; et al.	2013-01-10
Data Cells with Drivers and Methods of Making and Operating the Same App 20130005102 - Juengling; Werner	2013-01-03
Methods of forming an integrated circuit with self-aligned trench formation Grant 8,343,875 - Juengling , et al. January 1, 2	2013-01-01
Cross-hair Cell Based Floating Body Device App 20120309149 - Juengling; Werner	2012-12-06
Vertically stacked fin transistors and methods of fabricating and operating the same Grant 8,294,511 - Juengling October 23, 2	2012-10-23
Method of fabricating a finFET having cross-hair cells Grant 8,293,602 - Juengling October 23, 2	2012-10-23
Memory Device Comprising An Array Portion And A Logic Portion App 20120256272 - Juengling; Werner	2012-10-11
Cross-hair cell based floating body device Grant 8,278,703 - Juengling October 2, 2	2012-10-02
Locally 2 Sided Chc Dram Access Transistor Structure App 20120235214 - Juengling; Werner	2012-09-20
Multi-level Dram Cell Using Chc Technology App 20120236629 - Juengling; Werner	2012-09-20
Double Gated 4f2 Dram Chc Cell And Methods Of Fabricating The Same App 20120205719 - Juengling; Werner ; et al.	2012-08-16
Method And Algorithm For Random Half Pitched Interconnect Layout With Constant Spacing App 20120184106 - Juengling; Werner	2012-07-19
Memory device comprising an array portion and a logic portion Grant 8,207,583 - Juengling June 26, 2	2012-06-26
Semiconductor Device Comprising a Transistor Gate Having Multiple Vertically Oriented Sidewalls App 20120139039 - Juengling; Werner	2012-06-07
Vertically Stacked Fin Transistors And Methods Of Fabricating And Operating The Same App 20120126883 - Juengling; Werner	2012-05-24
Double Gated 4f2 Dram Chc Cell And Methods Of Fabricating The Same App 20120126885 - Juengling; Werner ; et al.	2012-05-24
Cross-hair Cell Devices And Methods For Manufacturing The Same App 20120126338 - Juengling; Werner	2012-05-24
Double Gated Fin Transistors And Methods Of Fabricating And Operating The Same App 20120126884 - Juengling; Werner	2012-05-24
Data Cells And Connections To Data Cells App 20120104488 - Juengling; Werner	2012-05-03
Methods Of Forming An Integrated Circuit With Self-aligned Trench Formation App 20120108069 - Juengling; Werner ; et al.	2012-05-03
Vertical Transistors App 20120094449 - Juengling; Werner	2012-04-19
Method and algorithm for random half pitched interconnect layout with constant spacing Grant 8,148,247 - Juengling April 3, 2	2012-04-03
Memory structure having volatile and non-volatile memory portions Grant 8,149,619 - Kirsch , et al. April 3, 2	2012-04-03
Transistor with a passive gate Grant 8,148,776 - Juengling April 3, 2	2012-04-03
Methods of providing electrical isolation and semiconductor structures including same Grant 8,148,775 - Gilgen , et al. April 3, 2	2012-04-03
Vertical Gated Access Transistor App 20120049246 - Juengling; Werner	2012-03-01
Systems and Devices Including Multi-Gate Transistors and Methods of Using, Making, and Operating the Same App 20120018789 - Juengling; Werner	2012-01-26
Self-aligned trench formation Grant 8,101,497 - Juengling , et al. January 24, 2	2012-01-24
Vertical transistors Grant 8,097,910 - Juengling January 17, 2	2012-01-17
Concentric or Nested Container Capacitor Structure for Integrated Circuits App 20110303957 - Juengling; Werner	2011-12-15
Methods of forming data cells and connections to data cells Grant 8,076,229 - Juengling December 13, 2	2011-12-13
Non-planar Thin Fin Transistor App 20110284960 - Juengling; Werner	2011-11-24
Digit Line Equilibration Using Access Devices At The Edge Of Sub Arrays App 20110267912 - Juengling; Werner	2011-11-03
Vertical gated access transistor Grant 8,039,348 - Juengling October 18, 2	2011-10-18
Data Cells with Drivers and Methods of Making and Operating the Same App 20110249488 - Juengling; Werner	2011-10-13
Concentric or nested container capacitor structure for integrated circuits Grant 8,017,985 - Juengling September 13, 2	2011-09-13
Floating Body Cell Structures, Devices Including Same, And Methods For Forming Same App 20110215408 - Tang; Sanh D. ; et al.	2011-09-08
Cross-hair Cell Based Floating Body Device App 20110193157 - Juengling; Werner	2011-08-11
Cross-hair Cell Wordline Formation App 20110193172 - Juengling; Werner	2011-08-11
Techniques for fabricating a non-planar transistor Grant 7,993,988 - Juengling August 9, 2	2011-08-09
Digit line equilibration using access devices at the edge of sub-arrays Grant 7,986,576 - Juengling July 26, 2	2011-07-26
Systems and devices including multi-gate transistors and methods of using, making, and operating the same Grant 7,981,736 - Juengling July 19, 2	2011-07-19
Integrated Circuits And Transistor Design Therefor App 20110169063 - Juengling; Werner	2011-07-14
Data cells with drivers and methods of making and operating the same Grant 7,969,776 - Juengling June 28, 2	2011-06-28
Devices with Cavity-Defined Gates and Methods of Making the Same App 20110143528 - Juengling; Werner	2011-06-16
Memory Device With Recessed Construction Between Memory Constructions App 20110133270 - Juengling; Werner	2011-06-09
Memory Structure Having Volatile And Non-volatile Memory Portions App 20110127596 - Kirsch; Howard C. ; et al.	2011-06-02
Memory Having A Vertical Access Device App 20110081757 - Juengling; Werner	2011-04-07
Semiconductor structure including gateline surrounding source and drain pillars Grant 7,915,692 - Juengling March 29, 2	2011-03-29
Devices with cavity-defined gates and methods of making the same Grant 7,915,659 - Juengling March 29, 2	2011-03-29
Two-sided surround access transistor for a 4.5F2 DRAM cell Grant 7,902,598 - Juengling March 8, 2	2011-03-08
Memory structure having volatile and non-volatile memory portions Grant 7,898,857 - Kirsch , et al. March 1, 2	2011-03-01
Memory Device Comprising An Array Portion And A Logic Portion App 20110042755 - Juengling; Werner	2011-02-24
Method And Algorithm For Random Half Pitched Interconnect Layout With Constant Spacing App 20110034024 - Juengling; Werner	2011-02-10
Concentric or Nested Container Capacitor Structure for Integrated Circuits App 20100327336 - Juengling; Werner	2010-12-30
Systems And Devices Including Multi-gate Transistors And Methods Of Using, Making, And Operating The Same App 20100323481 - Juengling; Werner	2010-12-23
Digit Line Equilibration Using Access Devices At The Edge Of Sub-arrays App 20100322025 - Juengling; Werner	2010-12-23
Masking process for simultaneously patterning separate regions Grant 7,842,558 - Juengling November 30, 2	2010-11-30
Vertical Transistors App 20100276749 - Juengling; Werner	2010-11-04
Methods of providing electrical isolation in semiconductor structures Grant 7,824,983 - Juengling November 2, 2	2010-11-02
Method and algorithm for random half pitched interconnect layout with constant spacing Grant 7,816,262 - Juengling October 19, 2	2010-10-19
Concentric or nested container capacitor structure for integrated circuits Grant 7,807,541 - Juengling October 5, 2	2010-10-05
Systems and devices including multi-gate transistors and methods of using, making, and operating the same Grant 7,808,042 - Juengling October 5, 2	2010-10-05
Systems And Devices Including Local Data Lines And Methods Of Using, Making, And Operating The Same App 20100238697 - Juengling; Werner	2010-09-23
Digit line equilibration using access devices at the edge of sub-arrays Grant 7,800,965 - Juengling September 21, 2	2010-09-21
Vertical Gated Access Transistor App 20100230733 - Juengling; Werner	2010-09-16
DRAM cells with vertical transistors Grant 7,772,633 - Juengling August 10, 2	2010-08-10
Systems and devices including local data lines and methods of using, making, and operating the same Grant 7,742,324 - Juengling June 22, 2	2010-06-22
Vertical gated access transistor Grant 7,736,980 - Juengling June 15, 2	2010-06-15
Methods Of Providing Electrical Isolation And Semiconductor Structures Including Same App 20100133609 - Gilgen; Brent D. ; et al.	2010-06-03
Transistor With A Passive Gate And Methods Of Fabricating The Same App 20100066440 - Juengling; Werner	2010-03-18
Self-aligned Trench Formation App 20100062579 - Juengling; Werner ; et al.	2010-03-11
Techniques For Fabricating A Non-planar Transistor App 20090298246 - Juengling; Werner	2009-12-03
Methods Of Providing Electrical Isolation And Semiconductor Structures Including Same App 20090294840 - Gilgen; Brent D. ; et al.	2009-12-03
Methods Of Forming Data Cells And Connections To Data Cells App 20090294842 - JUENGLING; Werner	2009-12-03
Reverse metal process for creating a metal silicide transistor gate structure Grant 7,601,598 - Juengling , et al. October 13, 2	2009-10-13
Data Cells With Drivers And Methods Of Making And Operating The Same App 20090251946 - Juengling; Werner	2009-10-08
Systems And Devices Including Multi-gate Transistors And Methods Of Using, Making, And Operating The Same App 20090238000 - Juengling; Werner	2009-09-24
Systems And Devices Including Multi-transistor Cells And Methods Of Using, Making, And Operating The Same App 20090238010 - Juengling; Werner	2009-09-24
Memory Structure Having Volatile And Non-volatile Memory Portions App 20090237996 - Kirsch; Howard C. ; et al.	2009-09-24
Digit Line Equilibration Using Access Devices At The Edge Of Sub-arrays App 20090225612 - Juengling; Werner	2009-09-10
Devices With Cavity-defined Gates And Methods Of Making The Same App 20090224357 - Juengling; Werner	2009-09-10
Systems And Devices Including Local Data Lines And Methods Of Using, Making, And Operating The Same App 20090207681 - Juengling; Werner	2009-08-20
Devices Including Fin Transistors Robust To Gate Shorts And Methods Of Making The Same App 20090206443 - Juengling; Werner	2009-08-20
Systems And Devices Including Fin Transistors And Methods Of Using, Making, And Operating The Same App 20090206400 - Juengling; Werner	2009-08-20
DRAM array and electronic system Grant 7,573,088 - Juengling August 11, 2	2009-08-11
Non-planar transistor and techniques for fabricating the same Grant 7,573,108 - Juengling August 11, 2	2009-08-11
Semiconductor structures and memory device constructions Grant 7,547,949 - Juengling June 16, 2	2009-06-16
Vertical Gated Access Transistor App 20090104744 - Juengling; Werner	2009-04-23
Dram Cells With Vertical Transistors App 20090096000 - Juengling; Werner	2009-04-16
DRAM cells with vertical transistors Grant 7,482,229 - Juengling January 27, 2	2009-01-27
Vertical gated access transistor Grant 7,476,933 - Juengling January 13, 2	2009-01-13
Methods of forming semiconductor constructions Grant 7,470,590 - Juengling , et al. December 30, 2	2008-12-30
Methods of forming DRAM arrays Grant 7,459,362 - Juengling December 2, 2	2008-12-02
DRAM cells with vertical transistors Grant 7,442,976 - Juengling October 28, 2	2008-10-28
Semiconductor Structures And Memory Device Constructions App 20080203453 - Juengling; Werner	2008-08-28
Semiconductor structures and memory device constructions Grant 7,391,070 - Juengling June 24, 2	2008-06-24
Method and apparatus for designing a pattern on a semiconductor surface Grant 7,370,306 - Juengling May 6, 2	2008-05-06
Methods of forming integrated circuitry and methods of forming local interconnects Grant 7,364,997 - Juengling April 29, 2	2008-04-29
Semiconductor structures Grant 7,335,964 - Juengling , et al. February 26, 2	2008-02-26
Semiconductor processing methods Grant 7,326,606 - Juengling February 5, 2	2008-02-05
Apparatus For A Self-aligned Recessed Access Device (rad) Transistor Gate App 20080012070 - Juengling; Werner	2008-01-17
Non-planar transistor and techniques for fabricating the same App 20070262375 - Juengling; Werner	2007-11-15
Pattern generation on a semiconductor surface Grant 7,290,242 - Juengling October 30, 2	2007-10-30
Reverse metal process for creating a metal silicide transistor gate structure Grant 7,288,817 - Juengling , et al. October 30, 2	2007-10-30
Method and apparatus for a self-aligned recessed access device (RAD) transistor gate Grant 7,282,401 - Juengling October 16, 2	2007-10-16
Masking process for simultaneously patterning separate regions App 20070205438 - Juengling; Werner	2007-09-06
Vertical gated access transistor App 20070205443 - Juengling; Werner	2007-09-06
Metal to polysilicon contact in oxygen environment Grant 7,262,473 - Juengling August 28, 2	2007-08-28
Semiconductor constructions Grant 7,262,503 - Juengling , et al. August 28, 2	2007-08-28
Semiconductor Constructions, Memory Cells, DRAM Arrays, Electronic Systems; Methods of Forming Semiconductor Constructions; and Methods of Forming DRAM Arrays App 20070181929 - Juengling; Werner	2007-08-09
Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry App 20070152340 - Juengling; Werner	2007-07-05
Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry Grant 7,235,480 - Juengling June 26, 2	2007-06-26
Methods for making nearly planar dielectric films in integrated circuits Grant 7,235,865 - Juengling June 26, 2	2007-06-26
Method and apparatus for a deposited fill layer App 20070141774 - Ireland; Philip J. ; et al.	2007-06-21
Method and apparatus for a deposited fill layer Grant 7,196,394 - Ireland , et al. March 27, 2	2007-03-27
Method and algorithm for random half pitched interconnect layout with constant spacing App 20070050748 - Juengling; Werner	2007-03-01
Method and apparatus for a self-aligned recessed access device (RAD) transistor gate App 20070010058 - Juengling; Werner	2007-01-11
Methods of forming integrated circuitry and methods of forming local interconnects App 20070010078 - Juengling; Werner	2007-01-11
Semiconductor constructions, memory cells, DRAM arrays, electronic systems; methods of forming semiconductor constructions; and methods of forming DRAM arrays App 20060289914 - Juengling; Werner	2006-12-28
Two-sided surround access transistor for a 4.5F2 DRAM cell App 20060289919 - Juengling; Werner	2006-12-28
Methods for making nearly planar dielectric films in integrated circuits App 20060261435 - Juengling; Werner	2006-11-23
DRAM cells with vertical transistors App 20060258109 - Juengling; Werner	2006-11-16
Methods For Making Nearly Planar Dielectric Films In Integrated Circuits App 20060246736 - Juengling; Werner	2006-11-02
Methods for making nearly planar dielectric films in integrated circuits Grant 7,125,800 - Juengling October 24, 2	2006-10-24
Methods of forming semiconductor constructions App 20060231528 - Juengling; Werner ; et al.	2006-10-19
Concentric or nested container capacitor structure for integrated circuits App 20060226496 - Juengling; Werner	2006-10-12
Concentric or nested container capacitor structure for integrated circuits App 20060226465 - Juengling; Werner	2006-10-12
Methods of forming semiconductor constructions Grant 7,115,512 - Juengling , et al. October 3, 2	2006-10-03
Methods of forming materials between conductive electrical components, and insulating materials Grant 7,112,542 - Juengling , et al. September 26, 2	2006-09-26
Methods for forming semiconductor structures Grant 7,098,105 - Juengling August 29, 2	2006-08-29
Semiconductor structures and memory device constructions App 20060189078 - Juengling; Werner	2006-08-24
Transistor gate structure Grant 7,067,880 - Juengling , et al. June 27, 2	2006-06-27
Fill pattern generation for spin-on glass and related self-planarization deposition Grant 7,026,717 - Juengling , et al. April 11, 2	2006-04-11
DRAM cells with vertical transistors App 20060046407 - Juengling; Werner	2006-03-02
Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry App 20060024933 - Juengling; Werner	2006-02-02
Semiconductor structures and memory device constructions App 20060011947 - Juengling; Werner	2006-01-19
Methods for making nearly planar dielectric films in integrated circuits App 20060001022 - Juengling; Werner	2006-01-05
Concentric or nested container capacitor structure for integrated cicuits App 20050280060 - Juengling, Werner	2005-12-22
Methods For Forming Semiconductor Structures App 20050277249 - Juengling, Werner	2005-12-15
Integrated circuitry App 20050263794 - Juengling, Werner	2005-12-01
Methods of forming semiconductor constructions App 20050255701 - Juengling, Werner ; et al.	2005-11-17
Semiconductor processing methods Grant 6,949,430 - Juengling September 27, 2	2005-09-27
Methods of forming materials over uneven surface topologies, and methods of forming insulative materials over and between conductive lines App 20050206003 - Juengling, Werner ; et al.	2005-09-22
Bit line contacts Grant 6,936,899 - Juengling August 30, 2	2005-08-30
Method and apparatus for designing a pattern on a semiconductor surface Grant 6,934,928 - Juengling August 23, 2	2005-08-23
Pattern generation on a semiconductor surface App 20050172249 - Juengling, Werner	2005-08-04
Semiconductor constructions App 20050121794 - Juengling, Werner ; et al.	2005-06-09
Reverse metal process for creating a metal silicide transistor gate structure App 20050124106 - Juengling, Werner ; et al.	2005-06-09
Pattern generation on a semiconductor surface Grant 6,898,779 - Juengling May 24, 2	2005-05-24
Method of forming minimally spaced word lines App 20050104090 - Juengling, Werner	2005-05-19
Methods of forming materials over uneven surface topologies, and methods of forming insulative materials over and between conductive lines Grant 6,890,858 - Juengling , et al. May 10, 2	2005-05-10
Disposable spacer App 20050072969 - Juengling, Werner	2005-04-07
Methods of forming materials between conductive electrical components, and insulating materials Grant 6,858,526 - Juengling , et al. February 22, 2	2005-02-22
Method and apparatus for designing a pattern on a semiconductor surface App 20050034092 - Juengling, Werner	2005-02-10
Methods for making nearly planar dielectric films in integrated circuits App 20050023695 - Juengling, Werner	2005-02-03
Minimally spaced gates and word lines Grant 6,844,594 - Juengling January 18, 2	2005-01-18
Fill pattern generation for spin-on glass and related self-planarization deposition App 20050001322 - Juengling, Werner ; et al.	2005-01-06
Low leakage diodes, including photodiodes Grant 6,838,714 - Rhodes , et al. January 4, 2	2005-01-04
Reverse metal process for creating a metal silicide transistor gate structure Grant 6,821,855 - Juengling , et al. November 23, 2	2004-11-23
Disposable spacer Grant 6,821,836 - Juengling November 23, 2	2004-11-23
Methods of forming materials between conductive electrical components, and insulating materials Grant 6,812,160 - Juengling , et al. November 2, 2	2004-11-02
Fill pattern generation for spin-on glass and related self-planarization deposition Grant 6,812,138 - Juengling , et al. November 2, 2	2004-11-02
Semiconductor processing methods App 20040214438 - Juengling, Werner	2004-10-28
Fill pattern generation for spin-on glass and related self-planarization deposition Grant 6,809,389 - Juengling , et al. October 26, 2	2004-10-26
Fill pattern generation for spin-on glass and related self-planarization deposition Grant 6,806,577 - Juengling , et al. October 19, 2	2004-10-19
Method of forming a metal to polysilicon contact in oxygen environment Grant 6,787,465 - Juengling September 7, 2	2004-09-07
Fill pattern generation for spin-on-glass and related self-planarization deposition Grant 6,777,813 - Juengling , et al. August 17, 2	2004-08-17
Disposable spacer and method of forming and using same Grant 6,777,297 - Juengling August 17, 2	2004-08-17
Fill pattern generation for spin-on glass and related self-planarization deposition App 20040155319 - Juengling, Werner ; et al.	2004-08-12
Fill pattern generation for spin-on glass and related self-planarization deposition App 20040157428 - Juengling, Werner ; et al.	2004-08-12
Fill pattern generation for spin-on glass and related self-planarization deposition App 20040157137 - Juengling, Werner ; et al.	2004-08-12
Method and apparatus for a deposited fill layer App 20040135227 - Ireland, Philip J. ; et al.	2004-07-15
Bit line contacts App 20040127018 - Juengling, Werner	2004-07-01
Metal to polysilicon contact in oxygen environment App 20040127022 - Juengling, Werner	2004-07-01
Semiconductor Processing Methods Of Forming Devices On A Substrate, Forming Device Arrays On A Substrate, Forming Conductive Lines On A Substrate, And Forming Capacitor Arrays On A Substrate, And Integrated Circuitry Grant 6,753,220 - Juengling June 22, 2	2004-06-22
Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts Grant 6,746,917 - Juengling June 8, 2	2004-06-08
Method of forming minimally spaced word lines App 20040105330 - Juengling, Werner	2004-06-03
Reverse metal process for creating a metal silicide transistor gate structure App 20040075150 - Juengling, Werner ; et al.	2004-04-22
Semiconductor processing methods of forming a contact opening to a conductive line and methods of forming substrate active area source/drain regions App 20040067611 - Juengling, Werner	2004-04-08
Methods for making nearly planar dielectric films in integrated circuits App 20040061196 - Juengling, Werner	2004-04-01
Reverse metal process for creating a metal silicide transistor gate structure App 20040043573 - Juengling, Werner ; et al.	2004-03-04
Pattern generation on a semiconductor surface App 20040044978 - Juengling, Werner	2004-03-04
Method and apparatus for designing a pattern on a semiconductor surface App 20040044980 - Juengling, Werner	2004-03-04
Fill pattern generation for spin-on glass and related self-planarization deposition App 20030168741 - Juengling, Werner ; et al.	2003-09-11
Methods of forming materials between conductive electrical components, and insulating materials App 20030134503 - Juengling, Werner ; et al.	2003-07-17
Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts App 20030064557 - Juengling, Werner	2003-04-03
Method of forming minimally spaced word lines App 20030059994 - Juengling, Werner	2003-03-27
Method of forming a metal to polysilicon contact in oxygen environment App 20030057467 - Juengling, Werner	2003-03-27
Semiconductor processing methods of forming devices on a substrate, forming device arrays on a substrate, forming conductive lines on a substrate, and forming capacitor arrays on a substrate, and integrated circuitry App 20030049902 - Juengling, Werner	2003-03-13
Methods of forming materials over uneven surface topologies, and methods of forming insulative materials over and between conductive lines App 20030040186 - Juengling, Werner ; et al.	2003-02-27
Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry App 20030027387 - Juengling, Werner	2003-02-06
Disposable spacer and method of forming and using same App 20030003750 - Juengling, Werner	2003-01-02
Disposable spacer and method of forming and using same App 20020173093 - Juengling, Werner	2002-11-21
Method for designing photolithographic reticle layout, reticle, and photolithographic process App 20020160278 - Winder, Amy A. ; et al.	2002-10-31
Method of forming minimally spaced word lines App 20020151179 - Juengling, Werner	2002-10-17
Method of making a metallization line layout App 20020121651 - Juengling, Werner	2002-09-05
Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts App 20020115261 - Juengling, Werner	2002-08-22
Semiconductor processing methods of forming a contact opening to a conductive line and methods of forming substrate active area source/drain regions App 20020115248 - Juengling, Werner	2002-08-22
Method of forming a metal to polysilicon contact in oxygen environment App 20020110987 - Juengling, Werner	2002-08-15
Contact Plug App 20020093099 - JUENGLING, WERNER ; et al.	2002-07-18
Dram Capacitor Array And Integrated Device Array Of Substantially Identically Shaped Devices App 20020052068 - JUENGLING, WERNER	2002-05-02
Semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts App 20020045308 - Juengling, Werner	2002-04-18
Method of forming a metal to polysilicon contact in oxygen environment App 20020025665 - Juengling, Werner	2002-02-28
Methods of forming materials between conductive electrical components, and insulating materials App 20020019125 - Juengling, Werner ; et al.	2002-02-14
Semiconductor Processing Methods Of Forming Devices On A Substrate, Forming Device Arrays On A Substrate, Forming Conductive Lines On A Substrate, And Forming Capacitor Arrays On A Substrate, And Integrated Circuitry App 20020009849 - JUENGLING, WERNER	2002-01-24
Methods of forming materials between conductive electrical components, and insulating materials App 20010050438 - Juengling, Werner ; et al.	2001-12-13
Methods of forming materials over uneven surface topologies, and methods of forming insulative materials over and between conductive lines App 20010027022 - Juengling, Werner ; et al.	2001-10-04
Semiconductor processing methods of forming integrated circuitry and semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry App 20010027000 - Juengling, Werner	2001-10-04
Methods of forming materials between conductive electrical components, and insulating materials App 20010019876 - Juengling, Werner ; et al.	2001-09-06
Optimized low leakage diodes, including photodiodes App 20010017382 - Rhodes, Howard E. ; et al.	2001-08-30
Semiconductor circuit design methods, semiconductor processing methods and integrated circuitry App 20010013115 - Juengling, Werner	2001-08-09
Methods Of Forming Materials Over Uneven Surface Topologies, And Methods Of Forming Insulative Materials Over And Between Conductive Lines App 20010001731 - JUENGLING, WERNER ; et al.	2001-05-24