Juchmes; Werner

Patent Applications and Registrations

Patent applications and USPTO patent grants for Juchmes; Werner.The latest application filed is for "digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal featu".

Company Profile

4.10.8

Juchmes; Werner - Boeblingen DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature Grant 11,043,938 - Barowski , et al. June 22, 2	2021-06-22
Analysis and modification of circuit designs Grant 10,984,160 - Schmidt , et al. April 20, 2	2021-04-20
Digital Logic Circuit For Deterring Race Violations At An Array Test Control Boundary Using An Inverted Array Clock Signal Featu App 20200127649 - Barowski; Harry ; et al.	2020-04-23
Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature Grant 10,587,248 - Barowski , et al.	2020-03-10
Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature Grant 10,367,481 - Barowski , et al. July 30, 2	2019-07-30
Digital Logic Circuit App 20180212595 - Barowski; Harry ; et al.	2018-07-26
Digital Logic Circuit App 20180212594 - Barowski; Harry ; et al.	2018-07-26
Content addressable memory array comprising geometric footprint and RAM cell block located between two parts of a CAM cell block Grant 9,666,278 - Fritsch , et al. May 30, 2	2017-05-30
Hierarchical negative bitline boost write assist for SRAM memory devices Grant 9,431,096 - Fritsch , et al. August 30, 2	2016-08-30
Content Addressable Memory Array App 20160099053 - Fritsch; Alexander ; et al.	2016-04-07
Reduced Leakage Banked Wordline Header App 20130128684 - Buettner; Stefan ; et al.	2013-05-23
Reduced power consumption memory circuitry Grant 8,422,313 - Buettner , et al. April 16, 2	2013-04-16
Reduced Power Consumption Memory Circuitry App 20120155188 - Buettner; Stefan ; et al.	2012-06-21
Test interface for memory elements Grant 7,844,871 - Brandt , et al. November 30, 2	2010-11-30
Test Interface For Memory Elements App 20100122128 - Brandt; Uwe ; et al.	2010-05-13
Bypass circuit for memory arrays Grant 7,558,138 - Ehrenreich , et al. July 7, 2	2009-07-07

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