| Patent | Date |
|---|
Method for manufacturing and structure for transistors with reduced gate to contact spacing
Grant 7,459,734 - Joyner , et al. December 2, 2 | 2008-12-02 |
Methods and apparatus for inducing stress in a semiconductor device
Grant 7,339,214 - Wasshuber , et al. March 4, 2 | 2008-03-04 |
Means for forming SOI
Grant 7,101,772 - Houston , et al. September 5, 2 | 2006-09-05 |
Methods and apparatus for inducing stress in a semiconductor device
App 20050029560 - Wasshuber, Christoph ; et al. | 2005-02-10 |
Method for manufacturing and structure for transistors with reduced gate to contact spacing
App 20040211992 - Joyner, Keith A. ; et al. | 2004-10-28 |
Methods and apparatus for inducing stress in a semiconductor device
Grant 6,806,151 - Wasshuber , et al. October 19, 2 | 2004-10-19 |
Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device
App 20040192027 - Houston, Theodore W. ; et al. | 2004-09-30 |
Process to improve Nwell-Nwell isolation with a blanket low dose high energy implant
App 20040169236 - Sridhar, Seetharaman ; et al. | 2004-09-02 |
Method for manufacturing and structure for transistors with reduced gate to contact spacing including etching to thin the spacers
Grant 6,767,777 - Joyner , et al. July 27, 2 | 2004-07-27 |
Semiconductor device with fully self-aligned local interconnects, and method for fabricating the device
Grant 6,737,347 - Houston , et al. May 18, 2 | 2004-05-18 |
Methods and apparatus for inducing stress in a semiconductor device
App 20030111699 - Wasshuber, Christoph ; et al. | 2003-06-19 |
Method for manufacturing and structure for transistors with reduced gate to contact spacing
App 20020106875 - Joyner, Keith A. ; et al. | 2002-08-08 |
Process to improve Nwell-Nwell isolation with a blanket low dose high energy implant
App 20020086499 - Sridhar, Seetharaman ; et al. | 2002-07-04 |
Means for forming SOI
App 20020086463 - Houston, Theodore W. ; et al. | 2002-07-04 |
Annealed porous silicon with epitaxial layer for SOI
Grant 6,376,285 - Joyner , et al. April 23, 2 | 2002-04-23 |
Variable porosity porous silicon isolation
Grant 6,376,859 - Swanson , et al. April 23, 2 | 2002-04-23 |
Organic sidewall spacers used with resist
Grant 6,228,747 - Joyner May 8, 2 | 2001-05-08 |
Method for forming an isolation structure in a substrate
Grant 6,214,699 - Joyner April 10, 2 | 2001-04-10 |
Self-aligned trenched-channel lateral-current-flow transistor
Grant 6,207,511 - Chapman , et al. March 27, 2 | 2001-03-27 |
Trench isolation of a CMOS structure
Grant 6,114,741 - Joyner , et al. September 5, 2 | 2000-09-05 |
Implant enhancement of titanium silicidation
Grant 6,004,871 - Kittl , et al. December 21, 1 | 1999-12-21 |
Mesa isolation Refill Process for Silicon on Insulator Technology Using Flowage Oxides as the Refill Material
Grant 5,882,981 - Rajgopal , et al. March 16, 1 | 1999-03-16 |
Varying the thickness of the surface silicon layer in a silicon-on-insulator substrate
Grant 5,548,149 - Joyner August 20, 1 | 1996-08-20 |
Systems and methods for controlling the temperature and uniformity of a wafer during a SIMOX implantation process
Grant 5,440,132 - Joyner , et al. August 8, 1 | 1995-08-08 |
Method for constructing semiconductor-on-insulator
Grant 5,429,955 - Joyner , et al. July 4, 1 | 1995-07-04 |
Varying the thickness of the surface silicon layer in a silicon-on-insulator substrate
Grant 5,364,800 - Joyner November 15, 1 | 1994-11-15 |
Reducing leakage current in silicon-on-insulator substrates
Grant 5,352,341 - Joyner October 4, 1 | 1994-10-04 |
Process for forming an electrical interconnection system on a semiconductor
Grant 4,507,851 - Joyner , et al. April 2, 1 | 1985-04-02 |
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