| Patent | Date |
|---|
Symmetric multiprocessing system with unified environment and distributed system functions wherein bus operations related storage spaces are mapped into a single system address space
Grant 6,125,436 - Bertone , et al. September 26, 2 | 2000-09-26 |
Symmetric multiprocessing system with unified environment and distributed system functions
Grant 5,956,522 - Bertone , et al. September 21, 1 | 1999-09-21 |
Adaptively generating timing signals for access to various memory devices based on stored profiles
Grant 5,809,340 - Bertone , et al. September 15, 1 | 1998-09-15 |
Symmetric multiprocessing system with unified environment and distributed system functions
Grant 5,522,069 - Bertone , et al. May 28, 1 | 1996-05-28 |
Symmetric multiprocessing system with unified environment and distributed system functions
Grant 5,517,648 - Bertone , et al. May 14, 1 | 1996-05-14 |
Emulation of CISC instructions by RISC instructions using two pipelined stages for overlapped CISC decoding and RISC execution
Grant 5,430,862 - Smith , et al. July 4, 1 | 1995-07-04 |
Processing unit having multiple synchronous bus for sharing access and regulating system bus access to synchronous bus
Grant 5,341,508 - Keeley , et al. August 23, 1 | 1994-08-23 |
Bus controller having state machine for translating commands and controlling accesses from system bus to synchronous bus having different bus protocols
Grant 5,341,495 - Joyce , et al. August 23, 1 | 1994-08-23 |
External procedure invocation apparatus utilizing internal branch vector interrupts and vector address generation, in a RISC chip
Grant 5,287,522 - Brown , et al. February 15, 1 | 1994-02-15 |
Method and apparatus for avoiding processor deadly embrace in a multiprocessor system
Grant 5,283,870 - Joyce , et al. February 1, 1 | 1994-02-01 |
Recovery method and apparatus for a pipelined processing unit of a multiprocessor system
Grant 5,193,181 - Barlow , et al. March 9, 1 | 1993-03-09 |
Method for reexecuting instruction by altering high bits of instruction address based upon result of a subtraction operation with stored low bits
Grant 5,148,530 - Joyce , et al. September 15, 1 | 1992-09-15 |
Apparatus and method for data group coherency in a tightly coupled data processing system with plural execution and data cache units
Grant 5,148,533 - Joyce , et al. September 15, 1 | 1992-09-15 |
Apparatus and method for simultaneous execution of a write instruction and a succeeding read instruction in a data processing system with a store through cache strategy
Grant 5,123,097 - Joyce , et al. June 16, 1 | 1992-06-16 |
Segment descriptor unit for performing static and dynamic address translation operations
Grant 5,053,951 - Nusinov , et al. October 1, 1 | 1991-10-01 |
Apparatus and method for address translation of non-aligned double word virtual addresses
Grant 5,051,894 - Phillips , et al. September 24, 1 | 1991-09-24 |
Multiprocessors on a single semiconductor chip
Grant 4,942,547 - Joyce , et al. July 17, 1 | 1990-07-17 |
High speed high density dynamic address translator
Grant 4,813,002 - Joyce , et al. March 14, 1 | 1989-03-14 |
Virtual cache system using page level number generating CAM to access other memories for processing requests relating to a page
Grant 4,785,398 - Joyce , et al. November 15, 1 | 1988-11-15 |
Least recently used replacement level generating apparatus
Grant 4,783,735 - Miu , et al. November 8, 1 | 1988-11-08 |
Distributed control store word architecture
Grant 4,670,835 - Kelly , et al. June 2, 1 | 1987-06-02 |
Control store memory read error resiliency method and apparatus
Grant 4,641,305 - Joyce , et al. February 3, 1 | 1987-02-03 |
Local bus interface for controlling information transfers between units in a central subsystem
Grant 4,323,967 - Peters , et al. April 6, 1 | 1982-04-06 |
Apparatus for performing the scientific add instruction
Grant 4,308,589 - Joyce , et al. December 29, 1 | 1981-12-29 |
Automatic rounding of floating point operands
Grant 4,295,203 - Joyce October 13, 1 | 1981-10-13 |
Word oriented high speed buffer memory system connected to a system bus
Grant 4,214,303 - Joyce , et al. July 22, 1 | 1980-07-22 |
Round robin replacement for a cache store
Grant 4,195,343 - Joyce March 25, 1 | 1980-03-25 |
First in first out activity queue for a cache store
Grant 4,195,340 - Joyce March 25, 1 | 1980-03-25 |
Initialization of cache store to assure valid data
Grant 4,195,341 - Joyce , et al. March 25, 1 | 1980-03-25 |
Multi-configurable cache store system
Grant 4,195,342 - Joyce , et al. March 25, 1 | 1980-03-25 |
Out of store indicator for a cache store in test mode
Grant 4,190,885 - Joyce , et al. February 26, 1 | 1980-02-26 |
Continuous updating of cache store
Grant 4,167,782 - Joyce , et al. September 11, 1 | 1979-09-11 |
Private cache-to-CPU interface in a bus oriented data processing system
Grant 4,161,024 - Joyce , et al. July 10, 1 | 1979-07-10 |
High speed buffer memory system with word prefetch
Grant 4,157,587 - Joyce , et al. June 5, 1 | 1979-06-05 |
Microword address branching bit arrangement
Grant 4,124,893 - Joyce , et al. November 7, 1 | 1978-11-07 |
Microprogram memory bank addressing system
Grant 4,118,773 - Raguin , et al. October 3, 1 | 1978-10-03 |
ROM-initializing apparatus
Grant 4,087,857 - Joyce , et al. May 2, 1 | 1978-05-02 |
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