JOSHI; Manish Chandra

Patent Applications and Registrations

Patent applications and USPTO patent grants for JOSHI; Manish Chandra.The latest application filed is for "circuits for power down leakage reduction in random-access memory".

Company Profile

5.7.8

JOSHI; Manish Chandra - Bangalore IN
Joshi; Manish Chandra - Bengaluru IN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Circuits For Power Down Leakage Reduction In Random-access Memory App 20220028449 - GUPTA; Ankur ; et al.	2022-01-27
Static random-access memory (SRAM) system with delay tuning and control and a method thereof Grant 11,017,848 - Jain , et al. May 25, 2	2021-05-25
Apparatus and methods for compensating for variations in fabrication process of component(s) in a memory Grant 10,998,018 - Ranjan , et al. May 4, 2	2021-05-04
Static Random-access Memory (sram) System With Delay Tuning And Control And A Method Thereof App 20210118494 - JAIN; Ambuj ; et al.	2021-04-22
Apparatus And Methods For Compensating For Variations In Fabrication Process Of Component(s) In A Memory App 20210110854 - RANJAN; Shubham ; et al.	2021-04-15
Methods and systems for performing decoding in finFET based memories Grant 10,672,443 - Gupta , et al.	2020-06-02
Methods And Systems For Performing Decoding In Finfet Based Memories App 20200075070 - GUPTA; Ankur ; et al.	2020-03-05
Memory providing signal buffering scheme for array and periphery signals and operating method of the same Grant 10,304,507 - Joshi , et al.	2019-05-28
System on-chip (SoC) device with dedicated clock generator for memory banks Grant 10,147,493 - Rana , et al. De	2018-12-04
Memory Providing Signal Buffering Scheme For Array And Periphery Signals And Operating Method Of The Same App 20180204607 - JOSHI; Manish Chandra ; et al.	2018-07-19
System On-chip (soc) Device With Dedicated Clock Generator For Memory Banks App 20180174657 - RANA; Parvinder Kumar ; et al.	2018-06-21
High performance two-port SRAM architecture using 8T high performance single port bit cell Grant 8,958,254 - Joshi , et al. February 17, 2	2015-02-17
High Performance Two-port Sram Architecture Using 8t High Performance Single-port Bit Cell App 20130215689 - Joshi; Manish Chandra ; et al.	2013-08-22

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