Joshi; Mandar S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Joshi; Mandar S..The latest application filed is for "context-aware enrollment for text independent speaker recognition".

Company Profile

1.12.7

Joshi; Mandar S. - Saratoga CA
Joshi; Mandar S. - Santa Clara CA
Joshi; Mandar S. - Aloha OR
Joshi; Mandar S. - Beaverton OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and apparatus for a power-efficient framework to maintain data synchronization of a mobile personal computer to simulate a connected scenario Grant 10,361,933 - Varshney , et al.	2019-07-23
Context-aware enrollment for text independent speaker recognition Grant 10,339,935 - Cilingir , et al.	2019-07-02
Context-aware Enrollment For Text Independent Speaker Recognition App 20180366124 - Cilingir; Gokcen ; et al.	2018-12-20
Mechanism and apparatus for seamless voice wake and speaker verification Grant 9,852,731 - Dadu , et al. December 26, 2	2017-12-26
Malware-proof Privacy Indicator App 20170263254 - DEWAN; PRASHANT ; et al.	2017-09-14
Mechanism And Apparatus For Seamless Voice Wake And Speaker Verification App 20170032784 - Dadu; Saurabh ; et al.	2017-02-02
Mechanism and apparatus for seamless voice wake and speaker verification Grant 9,445,209 - Dadu , et al. September 13, 2	2016-09-13
Mechanism And Apparatus For Seamless Voice Wake And Speaker Verification App 20150245154 - Dadu; Saurabh ; et al.	2015-08-27
Transition From Low Power Always Listening Mode To High Power Speech Recognition Mode App 20150221307 - Shah; Saurin ; et al.	2015-08-06
Method and apparatus for performing distributed simulation utilizing a simulation backplane Grant 7,319,947 - Khaira , et al. January 15, 2	2008-01-15
Logic verification in large systems Grant 7,171,347 - Khaira , et al. January 30, 2	2007-01-30
Logic Verification In Large Systems App 20030163297 - KHAIRA, MANPREET S. ; et al.	2003-08-28
Apparatus and method for caching lock conditions in a multi-processor system Grant 6,006,299 - Wang , et al. December 21, 1	1999-12-21
Apparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer system Grant 5,715,428 - Wang , et al. February 3, 1	1998-02-03
Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers Grant 5,680,572 - Akkary , et al. October 21, 1	1997-10-21
Methods and apparatus for caching data in a non-blocking manner using a plurality of fill buffers Grant 5,671,444 - Akkary , et al. September 23, 1	1997-09-23
Write combining buffer for sequentially addressed partial line operations originating from a single instruction Grant 5,630,075 - Joshi , et al. May 13, 1	1997-05-13
Method and apparatus for implementing a single clock cycle line replacement in a data cache unit Grant 5,526,510 - Akkary , et al. June 11, 1	1996-06-11

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