Jones; Erin C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Jones; Erin C..The latest application filed is for "polycrystalline sige junctions for advanced devices".

Company Profile

0.21.17

Jones; Erin C. - Corvallis OR
Jones; Erin C. - Tuckahoe NY
Jones, Erin C. - Tuchahoe NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Polycrystalline SiGe Junctions for advanced devices Grant 7,741,165 - Chan , et al. June 22, 2	2010-06-22
Low temperature fusion bonding with high surface energy using a wet chemical treatment Grant 7,713,837 - Chan , et al. May 11, 2	2010-05-11
Low temperature fusion bonding with high surface energy using a wet chemical treatment Grant 7,566,631 - Chan , et al. July 28, 2	2009-07-28
Polycrystalline SiGe Junctions for Advanced Devices App 20080248635 - Chan; Kevin Kok ; et al.	2008-10-09
Low Temperature Fusion Bonding With High Surface Energy Using A Wet Chemical Treatment App 20080227270 - Chan; Kevin K. ; et al.	2008-09-18
Polycrystalline SiGe junctions for advanced devices Grant 7,387,924 - Chan , et al. June 17, 2	2008-06-17
Method of fabricating semiconductor side wall fin Grant 7,361,556 - Adkisson , et al. April 22, 2	2008-04-22
Method of fabricating semiconductor side wall fin Grant 7,265,417 - Adkisson , et al. September 4, 2	2007-09-04
Method of fabricating semiconductor side wall fin App 20070026617 - Adkisson; James W. ; et al.	2007-02-01
SOI wafers with 30-100 .ANG. buried oxide (BOX) created by wafer bonding using 30-100 .ANG. thin oxide as bonding layer Grant 7,166,521 - Boyd , et al. January 23, 2	2007-01-23
Method of fabricating semiconductor side wall fin Grant 7,163,864 - Adkisson , et al. January 16, 2	2007-01-16
Polycrystalline SiGe junctions for advanced devices App 20070010076 - Chan; Kevin Kok ; et al.	2007-01-11
Polycrystalline SiGe junctions for advanced devices Grant 7,135,391 - Chan , et al. November 14, 2	2006-11-14
Double gate trench transistor Grant 7,112,845 - Adkisson , et al. September 26, 2	2006-09-26
Low temperature fusion bonding with high surface energy using a wet chemical treatment App 20060194414 - Chan; Kevin K. ; et al.	2006-08-31
Polycrystalline SiGe junctions for advanced devices App 20050260832 - Chan, Kevin Kok ; et al.	2005-11-24
SOI wafers with 30-100 A buried oxide (BOX) created by wafer bonding using 30-100 A thin oxide as bonding layer App 20050042841 - Boyd, Diane C. ; et al.	2005-02-24
Method of fabricating semiconductor side wall fin App 20050001216 - Adkisson, James W. ; et al.	2005-01-06
SOI wafers with 30-100 .ANG. buried oxide (BOX) created by wafer bonding using 30-100 .ANG. thin oxide as bonding layer Grant 6,835,633 - Boyd , et al. December 28, 2	2004-12-28
Self-aligned planar double-gate process by amorphization Grant 6,833,569 - Dokumaci , et al. December 21, 2	2004-12-21
Method for making multiple threshold voltage FET using multiple work-function gate materials Grant 6,797,553 - Adkisson , et al. September 28, 2	2004-09-28
Damascene double-gate FET Grant 6,762,101 - Chan , et al. July 13, 2	2004-07-13
Low temperature fusion bonding with high surface energy using a wet chemical treatment App 20040126993 - Chan, Kevin K. ; et al.	2004-07-01
Self-aligned planar double-gate process by amorphization App 20040121549 - Dokumaci, Omer H. ; et al.	2004-06-24
Damascene double-gate MOSFET structure and its fabrication method Grant 6,686,630 - Hanafi , et al. February 3, 2	2004-02-03
SOI wafers with 30-100 A buried oxide (box) created by wafer bonding using 30-100 A thin oxide as bonding layer App 20040018699 - Boyd, Diane C. ; et al.	2004-01-29
Damascene double-gate FET App 20030193070 - Chan, Kevin K. ; et al.	2003-10-16
Damascene double-gate FET Grant 6,580,132 - Chan , et al. June 17, 2	2003-06-17
Method for making multiple threshold voltage fet using multiple work-function gate materials App 20020177279 - Adkisson, James W. ; et al.	2002-11-28
Double gate trench transistor Grant 6,472,258 - Adkisson , et al. October 29, 2	2002-10-29
Double gate trench transistor App 20020140039 - Adkisson, James W. ; et al.	2002-10-03
Multiple threshold voltage FET using multiple work-function gate materials Grant 6,448,590 - Adkisson , et al. September 10, 2	2002-09-10
Damascene double-gate mosfet structure and its fabrication method App 20020105039 - Hanafi, Hussein Ibrahim ; et al.	2002-08-08
Vertical trench-formed dual-gate FET device structure and method for creation Grant 6,406,962 - Agnello , et al. June 18, 2	2002-06-18
Two-step MOSFET gate formation for high-density devices App 20020042183 - Chan, Kevin K. ; et al.	2002-04-11
Method utilizing CMP to fabricate double gate MOSFETS with conductive sidewall contacts Grant 6,339,002 - Chan , et al. January 15, 2	2002-01-15
Two-step MOSFET gate formation for high-density devices Grant 6,333,247 - Chan , et al. December 25, 2	2001-12-25
Method for protecting refractory metal thin film requiring high temperature processing in an oxidizing atmosphere and structure formed thereby App 20010019737 - Chan, Kevin K. ; et al.	2001-09-06

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