loadpatents
name:-0.0022101402282715
name:-0.029520034790039
name:-0.00062012672424316
Jones, Edwin R. Patent Filings

Jones, Edwin R.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Jones, Edwin R..The latest application filed is for "system and method of dynamic entitlement".

Company Profile
0.28.1
  • Jones, Edwin R. - Columbia SC
  • Jones; Edwin R. - Sunnyvale CA
  • Jones; Edwin R. - Los Altos Hill CA
  • Jones; Edwin R. - Los Altos Hills CA
  • Jones; Edwin R. - Suunyvale CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
System and method of dynamic entitlement
App 20050278640 - Jones, Edwin R. ;   et al.
2005-12-15
Optimization processing for integrated circuit physical design automation system using optimally switched fitness improvement algorithms
Grant 6,493,658 - Koford , et al. December 10, 2
2002-12-10
Hexagonal architecture
Grant 6,407,434 - Rostoker , et al. June 18, 2
2002-06-18
Cell placement representation and transposition for integrated circuit physical design automation system
Grant 6,155,725 - Scepanovic , et al. December 5, 2
2000-12-05
Triangular semiconductor or gate
Grant 6,097,073 - Rostoker , et al. August 1, 2
2000-08-01
Architecture having diamond shaped or parallelogram shaped cells
Grant 5,973,376 - Rostoker , et al. October 26, 1
1999-10-26
Method of cell placement for an integrated circuit chip comprising chaotic placement and moving windows
Grant 5,903,461 - Rostoker , et al. May 11, 1
1999-05-11
Tri-directional interconnect architecture for SRAM
Grant 5,889,329 - Rostoker , et al. March 30, 1
1999-03-30
Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system
Grant 5,875,117 - Jones , et al. February 23, 1
1999-02-23
Hexagonal sense cell architecture
Grant 5,872,380 - Rostoker , et al. February 16, 1
1999-02-16
Optimization processing for integrated circuit physical design automation system using parallel moving windows
Grant 5,870,313 - Boyle , et al. February 9, 1
1999-02-09
Triangular semiconductor NAND gate
Grant 5,864,165 - Rostoker , et al. January 26, 1
1999-01-26
Triangular semiconductor "AND" gate device
Grant 5,834,821 - Rostoker , et al. November 10, 1
1998-11-10
CAD for hexagonal architecture
Grant 5,822,214 - Rostoker , et al. October 13, 1
1998-10-13
Fail-safe distributive processing method for producing a highest fitness cell placement for an integrated circuit chip
Grant 5,815,403 - Jones , et al. September 29, 1
1998-09-29
Transistors having dynamically adjustable characteristics
Grant 5,811,863 - Rostoker , et al. September 22, 1
1998-09-22
Polydirectional non-orthoginal three layer interconnect architecture
Grant 5,808,330 - Rostoker , et al. September 15, 1
1998-09-15
Hexagonal SRAM architecture
Grant 5,801,422 - Rostoker , et al. September 1, 1
1998-09-01
Cell placement alteration apparatus for integrated circuit chip physical design automation system
Grant 5,793,644 - Koford , et al. August 11, 1
1998-08-11
Hexagonal architecture with triangular shaped cells
Grant 5,789,770 - Rostoker , et al. August 4, 1
1998-08-04
Method for producing integrated circuit chip having optimized cell placement
Grant 5,781,439 - Rostoker , et al. July 14, 1
1998-07-14
Hexagonal field programmable gate array architecture
Grant 5,777,360 - Rostoker , et al. July 7, 1
1998-07-07
Optimization processing for integrated circuit physical design automation system using optimally switched cost function computations
Grant 5,745,363 - Rostoker , et al. April 28, 1
1998-04-28
Hexagonal DRAM array
Grant 5,742,086 - Rostoker , et al. April 21, 1
1998-04-21
Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system
Grant 5,742,510 - Rostoker , et al. April 21, 1
1998-04-21
Microelectronic integrated circuit including triangular CMOS "nand" gate device
Grant 5,650,653 - Rostoker , et al. July 22, 1
1997-07-22
Computer implemented method for producing optimized cell placement for integrated circiut chip
Grant 5,636,125 - Rostoker , et al. June 3, 1
1997-06-03
Cell placement alteration apparatus for integrated circuit chip physical design automation system
Grant 5,557,533 - Koford , et al. September 17, 1
1996-09-17
Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing
Grant 5,495,419 - Rostoker , et al. February 27, 1
1996-02-27

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