Johnson; Frank Scott

Patent Applications and Registrations

Patent applications and USPTO patent grants for Johnson; Frank Scott.The latest application filed is for "semiconductor device with doped region adjacent isolation structure in extension region".

Company Profile

0.30.23

Johnson; Frank Scott - Saratoga Springs NY
Johnson; Frank Scott - Saratoga Spring NY
Johnson; Frank Scott - Wappingers Falls NY
Johnson; Frank Scott - Wappinger Falls NY
Johnson; Frank Scott - Richardson TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor device with doped region adjacent isolation structure in extension region Grant 11,195,947 - Singh , et al. December 7, 2	2021-12-07
Semiconductor Device With Doped Region Adjacent Isolation Structure In Extension Region App 20210126126 - Singh; Jagar ; et al.	2021-04-29
Methods for converting planar designs to FinFET designs in the design and fabrication of integrated circuits Grant 9,336,345 - Tan , et al. May 10, 2	2016-05-10
Semiconductor structures and methods for forming isolation between Fin structures of FinFET devices Grant 9,257,325 - Knorr , et al. February 9, 2	2016-02-09
Method for forming and integrating metal gate transistors having self-aligned contacts and related structure Grant 9,000,534 - Knorr , et al. April 7, 2	2015-04-07
Methods For Converting Planar Designs To Finfet Designs In The Design And Fabrication Of Integrated Circuits App 20150093910 - Tan; Soon Yoeng ; et al.	2015-04-02
Semiconductor device with stressed fin sections Grant 8,912,603 - Luning , et al. December 16, 2	2014-12-16
Methods for forming semiconductor structures using selectively-formed sidewall spacers Grant 8,865,596 - Johnson October 21, 2	2014-10-21
Integrated circuits including multi-gate transistors locally interconnected by continuous fin structure and methods for the fabrication thereof Grant 8,729,609 - Johnson , et al. May 20, 2	2014-05-20
Methods for fabricating FinFET integrated circuits on bulk semiconductor substrates Grant 8,603,893 - Wei , et al. December 10, 2	2013-12-10
Methods For Fabricating Finfet Integrated Circuits On Bulk Semiconductor Substrates App 20130309838 - Wei; Andy C. ; et al.	2013-11-21
Methods For Forming Semiconductor Structures Using Selectively-formed Sidewall Spacers App 20130143409 - JOHNSON; Frank Scott	2013-06-06
Methods for forming semiconductor structures using selectively-formed sidewall spacers Grant 8,383,503 - Johnson February 26, 2	2013-02-26
Methods for fabricating non-planar electronic devices having sidewall spacers formed adjacent selected surfaces Grant 8,192,641 - Johnson June 5, 2	2012-06-05
Method of forming sidewall spacers to reduce formation of recesses in the substrate and increase dopant retention in a semiconductor device Grant 8,138,045 - Nandakumar , et al. March 20, 2	2012-03-20
Semiconductor Device With Stressed Fin Sections App 20110266622 - Luning; Scott ; et al.	2011-11-03
Methods for fabricating non-planar semiconductor devices having stress memory Grant 8,039,349 - Hargrove , et al. October 18, 2	2011-10-18
Methods for fabricating bulk FinFET devices having deep trench isolation Grant 8,039,326 - Knorr , et al. October 18, 2	2011-10-18
Semiconductor device with stressed fin sections, and related fabrication methods Grant 8,030,144 - Luning , et al. October 4, 2	2011-10-04
Integrated Circuits Including Multi-gate Transistors Locally Interconnected By Continuous Fin Structure And Methods For The Fabrication Thereof App 20110204419 - JOHNSON; Frank Scott ; et al.	2011-08-25
Method for fabricating a semiconductor device having a semiconductive resistor structure Grant 7,985,639 - Johnson , et al. July 26, 2	2011-07-26
FinFET structures with stress-inducing source/drain-forming spacers and methods for fabricating the same Grant 7,977,174 - Luning , et al. July 12, 2	2011-07-12
Methods for fabricating FinFET structures having different channel lengths Grant 7,960,287 - Johnson , et al. June 14, 2	2011-06-14
System and method for making photomasks Grant 7,930,656 - Aton , et al. April 19, 2	2011-04-19
Semiconductor Device With Stressed Fin Sections, And Related Fabrication Methods App 20110084336 - LUNING; Scott ; et al.	2011-04-14
Method For Fabricating A Semiconductor Device Having A Semiconductive Resistor Structure App 20110070712 - JOHNSON; Frank Scott ; et al.	2011-03-24
Semiconductor Structures And Methods For Forming Isolation Between Fin Structures Of Finfet Devices App 20110068431 - KNORR; Andreas ; et al.	2011-03-24
Reducing gate CD bias in CMOS processing Grant 7,910,422 - Mehrad , et al. March 22, 2	2011-03-22
Methods For Fabricating Bulk Finfet Devices Having Deep Trench Isolation App 20110045648 - KNORR; Andreas ; et al.	2011-02-24
Methods For Forming Semiconductor Structures Using Selectively-formed Sidewall Spacers App 20110034020 - JOHNSON; Frank Scott	2011-02-10
Methods For Fabricating Non-planar Semiconductor Devices Having Stress Memory App 20110027978 - HARGROVE; Michael J. ; et al.	2011-02-03
Methods For Fabricating Non-planar Electronic Devices Having Sidewall Spacers Formed Adjacent Selected Surfaces App 20110021027 - JOHNSON; Frank Scott	2011-01-27
Method for forming and integrating metal gate transistors having self-aligned contacts and related structure App 20100320509 - Knorr; Andreas H. ; et al.	2010-12-23
Method of forming source and drain regions utilizing dual capping layers and split thermal processes Grant 7,785,970 - Johnson , et al. August 31, 2	2010-08-31
Method of forming a silicided gate utilizing a CMP stack Grant 7,763,540 - Johnson , et al. July 27, 2	2010-07-27
Methods for fabricating FinFET structures having different channel lengths Grant 7,687,339 - Schultz , et al. March 30, 2	2010-03-30
Method Of Forming Sidewall Spacers To Reduce Formation Of Recesses In The Substrate And Increase Dopant Retention In A Semiconductor Device App 20090286375 - Nandakumar; Mahalingam ; et al.	2009-11-19
Reducing Gate Cd Bias In Cmos Processing App 20090166629 - Mehrad; Freidoon ; et al.	2009-07-02
System And Method For Making Photomasks App 20090125865 - Aton; Thomas J. ; et al.	2009-05-14
Method And Apparatus For De-interlacing Video Data App 20090053865 - Johnson; Frank Scott ; et al.	2009-02-26
Method of Forming a Silicided Gate Utilizing a CMP Stack App 20080268631 - Johnson; Frank Scott ; et al.	2008-10-30
Process method to optimize fully silicided gate (FUSI) thru PAI implant App 20080206973 - Johnson; Frank Scott ; et al.	2008-08-28
One mask PNP (or NPN) transistor allowing high performance Grant 6,797,577 - Johnson , et al. September 28, 2	2004-09-28
One mask PNP (OR NPN) transistor allowing high performance App 20040051148 - Johnson, Frank Scott ; et al.	2004-03-18

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.