loadpatents
name:-0.026742935180664
name:-0.016053915023804
name:-0.00053882598876953
Johnson; Charles Luther Patent Filings

Johnson; Charles Luther

Patent Applications and Registrations

Patent applications and USPTO patent grants for Johnson; Charles Luther.The latest application filed is for "hybrid bonding techniques for multi-layer semiconductor stacks".

Company Profile
0.11.6
  • Johnson; Charles Luther - Rochester MN US
  • Johnson; Charles Luther - Tampa FL US
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Universal inter-layer interconnect for multi-layer semiconductor stacks
Grant 9,495,498 - Bartley , et al. November 15, 2
2016-11-15
Hybrid bonding techniques for multi-layer semiconductor stacks
Grant 8,736,068 - Bartley , et al. May 27, 2
2014-05-27
Thermal enhancement for multi-layer semiconductor stacks
Grant 8,445,918 - Bartley , et al. May 21, 2
2013-05-21
Hybrid Bonding Techniques For Multi-layer Semiconductor Stacks
App 20130011968 - Bartley; Gerald K. ;   et al.
2013-01-10
Universal Inter-layer Interconnect For Multi-layer Semiconductor Stacks
App 20130009324 - Bartley; Gerald K. ;   et al.
2013-01-10
Universal inter-layer interconnect for multi-layer semiconductor stacks
Grant 8,330,489 - Bartley , et al. December 11, 2
2012-12-11
Hybrid bonding techniques for multi-layer semiconductor stacks
Grant 8,293,578 - Bartley , et al. October 23, 2
2012-10-23
Universal Inter-layer Interconnect For Multi-layer Semiconductor Stacks
App 20120198406 - Bartley; Gerald K. ;   et al.
2012-08-02
Hybrid Bonding Techniques For Multi-layer Semiconductor Stacks
App 20120187570 - Bartley; Gerald K. ;   et al.
2012-07-26
Hybrid Bonding Techniques For Multi-layer Semiconductor Stacks
App 20120098140 - Bartley; Gerald K. ;   et al.
2012-04-26
Universal Inter-Layer Interconnect for Multi-Layer Semiconductor Stacks
App 20100271071 - Bartley; Gerald K. ;   et al.
2010-10-28
SRAM that can be clocked on either clock phase
Grant 6,260,164 - Aipperspach , et al. July 10, 2
2001-07-10
Method and apparatus for single phase clock distribution with minimal clock skew
Grant 5,911,063 - Allen , et al. June 8, 1
1999-06-08
Pipelined memory interface and method for using the same
Grant 5,790,838 - Irish , et al. August 4, 1
1998-08-04

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